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git01.mediatek.com / filogic / uboot / cfa0e161e21bbd020509e70a1d43ba6d57c66290 / . / arch / arm / dts / dra76-evm-u-boot.dtsi
blob: c8da3e48389874d78173735a89f410a652efeccf [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
7
8&cpsw_emac0 {
9 phy-handle = <&dp83867_0>;
10};
11
12&cpsw_emac1 {
13 phy-handle = <&dp83867_1>;
14};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]15
16&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]18};
19
20&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]22};
23
24&mmc2_iodelay_hs200_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]26};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]27
28&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]30};
31
32&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]34 dr_mode = "peripheral";
35};
36
37&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]39};
40
41&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]43};