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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / dra76-evm-u-boot.dtsi
blob: db5a466d84a23dc973f1e0436e48b68ac83ea812 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]2/*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
Keerthy5d339ff2022-01-27 13:16:59 +0100[diff] [blame]7#include "dra7-ipu-common-early-boot.dtsi"
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]8
9&cpsw_emac0 {
10 phy-handle = <&dp83867_0>;
11};
12
13&cpsw_emac1 {
14 phy-handle = <&dp83867_1>;
15};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]16
17&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]18 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]19};
20
21&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]22 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]23};
24
25&mmc2_iodelay_hs200_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]26 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]27};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]28
29&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]30 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]31};
32
33&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]34 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]35 dr_mode = "peripheral";
36};
37
38&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]39 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]40};
41
42&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]43 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]44};