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git01.mediatek.com / filogic / uboot / cf08d1baa108ec6159ce040e2273cdfb88057bb3 / . / arch / arm / dts / imx6qdl-gw560x.dtsi
blob: 0786b0d5463a78ad19cfc80f540bc46490458294 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1/*
2 * Copyright 2017 Gateworks Corporation
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/input.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51
52/ {
53 /* these are used by bootloader for disabling nodes */
54 aliases {
55 led0 = &led0;
56 led1 = &led1;
57 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame^]58 mmc0 = &usdhc2;
59 mmc1 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]60 ssi0 = &ssi1;
61 usb0 = &usbh1;
62 usb1 = &usbotg;
63 };
64
65 chosen {
66 stdout-path = &uart2;
67 };
68
69 backlight-display {
70 compatible = "pwm-backlight";
71 pwms = <&pwm4 0 5000000>;
72 brightness-levels = <
73 0 1 2 3 4 5 6 7 8 9
74 10 11 12 13 14 15 16 17 18 19
75 20 21 22 23 24 25 26 27 28 29
76 30 31 32 33 34 35 36 37 38 39
77 40 41 42 43 44 45 46 47 48 49
78 50 51 52 53 54 55 56 57 58 59
79 60 61 62 63 64 65 66 67 68 69
80 70 71 72 73 74 75 76 77 78 79
81 80 81 82 83 84 85 86 87 88 89
82 90 91 92 93 94 95 96 97 98 99
83 100
84 >;
85 default-brightness-level = <100>;
86 };
87
88 backlight-keypad {
89 compatible = "gpio-backlight";
90 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
91 default-on;
92 };
93
94 gpio-keys {
95 compatible = "gpio-keys";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 user-pb {
100 label = "user_pb";
101 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
102 linux,code = <BTN_0>;
103 };
104
105 user-pb1x {
106 label = "user_pb1x";
107 linux,code = <BTN_1>;
108 interrupt-parent = <&gsc>;
109 interrupts = <0>;
110 };
111
112 key-erased {
113 label = "key-erased";
114 linux,code = <BTN_2>;
115 interrupt-parent = <&gsc>;
116 interrupts = <1>;
117 };
118
119 eeprom-wp {
120 label = "eeprom_wp";
121 linux,code = <BTN_3>;
122 interrupt-parent = <&gsc>;
123 interrupts = <2>;
124 };
125
126 tamper {
127 label = "tamper";
128 linux,code = <BTN_4>;
129 interrupt-parent = <&gsc>;
130 interrupts = <5>;
131 };
132
133 switch-hold {
134 label = "switch_hold";
135 linux,code = <BTN_5>;
136 interrupt-parent = <&gsc>;
137 interrupts = <7>;
138 };
139 };
140
141 leds {
142 compatible = "gpio-leds";
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_gpio_leds>;
145
146 led0: user1 {
147 label = "user1";
148 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
149 default-state = "on";
150 linux,default-trigger = "heartbeat";
151 };
152
153 led1: user2 {
154 label = "user2";
155 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
156 default-state = "off";
157 };
158
159 led2: user3 {
160 label = "user3";
161 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
162 default-state = "off";
163 };
164 };
165
166 memory@10000000 {
167 device_type = "memory";
168 reg = <0x10000000 0x40000000>;
169 };
170
171 pps {
172 compatible = "pps-gpio";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_pps>;
175 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
176 };
177
178 reg_2p5v: regulator-2p5v {
179 compatible = "regulator-fixed";
180 regulator-name = "2P5V";
181 regulator-min-microvolt = <2500000>;
182 regulator-max-microvolt = <2500000>;
183 regulator-always-on;
184 };
185
186 reg_3p3v: regulator-3p3v {
187 compatible = "regulator-fixed";
188 regulator-name = "3P3V";
189 regulator-min-microvolt = <3300000>;
190 regulator-max-microvolt = <3300000>;
191 regulator-always-on;
192 };
193
194 reg_5p0v: regulator-5p0v {
195 compatible = "regulator-fixed";
196 regulator-name = "5P0V";
197 regulator-min-microvolt = <5000000>;
198 regulator-max-microvolt = <5000000>;
199 regulator-always-on;
200 };
201
202 reg_12p0v: regulator-12p0v {
203 compatible = "regulator-fixed";
204 regulator-name = "12P0V";
205 regulator-min-microvolt = <12000000>;
206 regulator-max-microvolt = <12000000>;
207 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
208 enable-active-high;
209 };
210
211 reg_1p4v: regulator-vddsoc {
212 compatible = "regulator-fixed";
213 regulator-name = "vdd_soc";
214 regulator-min-microvolt = <1400000>;
215 regulator-max-microvolt = <1400000>;
216 regulator-always-on;
217 };
218
219 reg_usb_h1_vbus: regulator-usb-h1-vbus {
220 compatible = "regulator-fixed";
221 regulator-name = "usb_h1_vbus";
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5000000>;
224 regulator-always-on;
225 };
226
227 reg_usb_otg_vbus: regulator-usb-otg-vbus {
228 compatible = "regulator-fixed";
229 regulator-name = "usb_otg_vbus";
230 regulator-min-microvolt = <5000000>;
231 regulator-max-microvolt = <5000000>;
232 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
233 enable-active-high;
234 };
235
236 sound {
237 compatible = "fsl,imx6q-ventana-sgtl5000",
238 "fsl,imx-audio-sgtl5000";
239 model = "sgtl5000-audio";
240 ssi-controller = <&ssi1>;
241 audio-codec = <&sgtl5000>;
242 audio-routing =
243 "MIC_IN", "Mic Jack",
244 "Mic Jack", "Mic Bias",
245 "Headphone Jack", "HP_OUT";
246 mux-int-port = <1>;
247 mux-ext-port = <4>;
248 };
249};
250
251&audmux {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_audmux>;
254 status = "okay";
255};
256
257&ecspi3 {
258 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_ecspi3>;
261 status = "okay";
262};
263
264&can1 {
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_flexcan>;
267 status = "okay";
268};
269
270&clks {
271 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
272 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
273 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
274 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
275};
276
277&fec {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_enet>;
280 phy-mode = "rgmii-id";
281 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
282 status = "okay";
283};
284
285&hdmi {
286 ddc-i2c-bus = <&i2c3>;
287 status = "okay";
288};
289
290&i2c1 {
291 clock-frequency = <100000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c1>;
294 status = "okay";
295
296 gsc: gsc@20 {
297 compatible = "gw,gsc";
298 reg = <0x20>;
299 interrupt-parent = <&gpio1>;
300 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
301 interrupt-controller;
302 #interrupt-cells = <1>;
303 #size-cells = <0>;
304
305 adc {
306 compatible = "gw,gsc-adc";
307 #address-cells = <1>;
308 #size-cells = <0>;
309
310 channel@0 {
311 gw,mode = <0>;
312 reg = <0x00>;
313 label = "temp";
314 };
315
316 channel@2 {
317 gw,mode = <1>;
318 reg = <0x02>;
319 label = "vdd_vin";
320 };
321
322 channel@5 {
323 gw,mode = <1>;
324 reg = <0x05>;
325 label = "vdd_3p3";
326 };
327
328 channel@8 {
329 gw,mode = <1>;
330 reg = <0x08>;
331 label = "vdd_bat";
332 };
333
334 channel@b {
335 gw,mode = <1>;
336 reg = <0x0b>;
337 label = "vdd_5p0";
338 };
339
340 channel@e {
341 gw,mode = <1>;
342 reg = <0xe>;
343 label = "vdd_arm";
344 };
345
346 channel@11 {
347 gw,mode = <1>;
348 reg = <0x11>;
349 label = "vdd_soc";
350 };
351
352 channel@14 {
353 gw,mode = <1>;
354 reg = <0x14>;
355 label = "vdd_3p0";
356 };
357
358 channel@17 {
359 gw,mode = <1>;
360 reg = <0x17>;
361 label = "vdd_1p5";
362 };
363
364 channel@1d {
365 gw,mode = <1>;
366 reg = <0x1d>;
367 label = "vdd_1p8";
368 };
369
370 channel@20 {
371 gw,mode = <1>;
372 reg = <0x20>;
373 label = "vdd_an1";
374 };
375
376 channel@23 {
377 gw,mode = <1>;
378 reg = <0x23>;
379 label = "vdd_2p5";
380 };
381
382 channel@26 {
383 gw,mode = <1>;
384 reg = <0x26>;
385 label = "vdd_gps";
386 };
387
388 channel@29 {
389 gw,mode = <1>;
390 reg = <0x29>;
391 label = "vdd_an2";
392 };
393 };
394 };
395
396 gsc_gpio: gpio@23 {
397 compatible = "nxp,pca9555";
398 reg = <0x23>;
399 gpio-controller;
400 #gpio-cells = <2>;
401 interrupt-parent = <&gsc>;
402 interrupts = <4>;
403 };
404
405 eeprom1: eeprom@50 {
406 compatible = "atmel,24c02";
407 reg = <0x50>;
408 pagesize = <16>;
409 };
410
411 eeprom2: eeprom@51 {
412 compatible = "atmel,24c02";
413 reg = <0x51>;
414 pagesize = <16>;
415 };
416
417 eeprom3: eeprom@52 {
418 compatible = "atmel,24c02";
419 reg = <0x52>;
420 pagesize = <16>;
421 };
422
423 eeprom4: eeprom@53 {
424 compatible = "atmel,24c02";
425 reg = <0x53>;
426 pagesize = <16>;
427 };
428
429 ds1672: rtc@68 {
430 compatible = "dallas,ds1672";
431 reg = <0x68>;
432 };
433};
434
435&i2c2 {
436 clock-frequency = <100000>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_i2c2>;
439 status = "okay";
440
441 sgtl5000: codec@a {
442 compatible = "fsl,sgtl5000";
443 reg = <0x0a>;
444 #sound-dai-cells = <0>;
445 clocks = <&clks IMX6QDL_CLK_CKO>;
446 VDDA-supply = <&reg_1p8v>;
447 VDDIO-supply = <&reg_3p3v>;
448 };
449
450 magn@1c {
451 compatible = "st,lsm9ds1-magn";
452 reg = <0x1c>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_mag>;
455 interrupt-parent = <&gpio5>;
456 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
457 };
458
459 tca8418: keypad@34 {
460 compatible = "ti,tca8418";
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_keypad>;
463 reg = <0x34>;
464 interrupt-parent = <&gpio5>;
465 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
466 linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
467 MATRIX_KEY(0x00, 0x00, BTN_1)
468 MATRIX_KEY(0x01, 0x01, BTN_2)
469 MATRIX_KEY(0x01, 0x00, BTN_3)
470 MATRIX_KEY(0x02, 0x00, BTN_4)
471 MATRIX_KEY(0x00, 0x03, BTN_5)
472 MATRIX_KEY(0x00, 0x02, BTN_6)
473 MATRIX_KEY(0x01, 0x03, BTN_7)
474 MATRIX_KEY(0x01, 0x02, BTN_8)
475 MATRIX_KEY(0x02, 0x02, BTN_9)
476 >;
477 keypad,num-rows = <4>;
478 keypad,num-columns = <4>;
479 };
480
481 ltc3676: pmic@3c {
482 compatible = "lltc,ltc3676";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_pmic>;
485 reg = <0x3c>;
486 interrupt-parent = <&gpio1>;
487 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
488
489 regulators {
490 /* VDD_DDR (1+R1/R2 = 2.105) */
491 reg_vdd_ddr: sw2 {
492 regulator-name = "vddddr";
493 regulator-min-microvolt = <868310>;
494 regulator-max-microvolt = <1684000>;
495 lltc,fb-voltage-divider = <221000 200000>;
496 regulator-ramp-delay = <7000>;
497 regulator-boot-on;
498 regulator-always-on;
499 };
500
501 /* VDD_ARM (1+R1/R2 = 1.931) */
502 reg_vdd_arm: sw3 {
503 regulator-name = "vddarm";
504 regulator-min-microvolt = <796551>;
505 regulator-max-microvolt = <1544827>;
506 lltc,fb-voltage-divider = <243000 261000>;
507 regulator-ramp-delay = <7000>;
508 regulator-boot-on;
509 regulator-always-on;
510 linux,phandle = <&reg_vdd_arm>;
511 };
512
513 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
514 reg_1p8v: sw4 {
515 regulator-name = "vdd1p8";
516 regulator-min-microvolt = <1033310>;
517 regulator-max-microvolt = <2004000>;
518 lltc,fb-voltage-divider = <301000 200000>;
519 regulator-ramp-delay = <7000>;
520 regulator-boot-on;
521 regulator-always-on;
522 };
523
524 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
525 reg_1p0v: ldo2 {
526 regulator-name = "vdd1p0";
527 regulator-min-microvolt = <950000>;
528 regulator-max-microvolt = <1050000>;
529 lltc,fb-voltage-divider = <78700 200000>;
530 regulator-boot-on;
531 regulator-always-on;
532 };
533
534 /* VDD_AUD_1P8: Audio codec */
535 reg_aud_1p8v: ldo3 {
536 regulator-name = "vdd1p8a";
537 regulator-min-microvolt = <1800000>;
538 regulator-max-microvolt = <1800000>;
539 regulator-boot-on;
540 };
541
542 /* VDD_HIGH (1+R1/R2 = 4.17) */
543 reg_3p0v: ldo4 {
544 regulator-name = "vdd3p0";
545 regulator-min-microvolt = <3023250>;
546 regulator-max-microvolt = <3023250>;
547 lltc,fb-voltage-divider = <634000 200000>;
548 regulator-boot-on;
549 regulator-always-on;
550 };
551 };
552 };
553
554 imu@6a {
555 compatible = "st,lsm9ds1-imu";
556 reg = <0x6a>;
557 st,drdy-int-pin = <1>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_imu>;
560 interrupt-parent = <&gpio5>;
561 interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
562 };
563};
564
565&i2c3 {
566 clock-frequency = <100000>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_i2c3>;
569 status = "okay";
570
571 egalax_ts: touchscreen@4 {
572 compatible = "eeti,egalax_ts";
573 reg = <0x04>;
574 interrupt-parent = <&gpio5>;
575 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
576 wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
577 };
578};
579
580&ldb {
581 fsl,dual-channel;
582 status = "okay";
583
584 lvds-channel@0 {
585 fsl,data-mapping = "spwg";
586 fsl,data-width = <18>;
587 status = "okay";
588
589 display-timings {
590 native-mode = <&timing0>;
591 timing0: hsd100pxn1 {
592 clock-frequency = <65000000>;
593 hactive = <1024>;
594 vactive = <768>;
595 hback-porch = <220>;
596 hfront-porch = <40>;
597 vback-porch = <21>;
598 vfront-porch = <7>;
599 hsync-len = <60>;
600 vsync-len = <10>;
601 };
602 };
603 };
604};
605
606&pcie {
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_pcie>;
609 reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
610 status = "okay";
611};
612
613&pwm2 {
614 pinctrl-names = "default";
615 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
616 status = "disabled";
617};
618
619&pwm3 {
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
622 status = "disabled";
623};
624
625&pwm4 {
626 #pwm-cells = <2>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&pinctrl_pwm4>;
629 status = "okay";
630};
631
632&ssi1 {
633 status = "okay";
634};
635
636&uart1 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_uart1>;
639 uart-has-rtscts;
640 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
641 status = "okay";
642};
643
644&uart2 {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_uart2>;
647 status = "okay";
648};
649
650&uart5 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_uart5>;
653 status = "okay";
654};
655
656&usbotg {
657 vbus-supply = <&reg_usb_otg_vbus>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&pinctrl_usbotg>;
660 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]661 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]662 status = "okay";
663};
664
665&usbh1 {
666 vbus-supply = <&reg_usb_h1_vbus>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&pinctrl_usbh1>;
669 status = "okay";
670};
671
672&usdhc2 {
673 pinctrl-names = "default";
674 pinctrl-0 = <&pinctrl_usdhc2>;
675 bus-width = <8>;
676 vmmc-supply = <&reg_3p3v>;
677 non-removable;
678 status = "okay";
679};
680
681&usdhc3 {
682 pinctrl-names = "default", "state_100mhz", "state_200mhz";
683 pinctrl-0 = <&pinctrl_usdhc3>;
684 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
685 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
686 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
687 vmmc-supply = <&reg_3p3v>;
688 status = "okay";
689};
690
691&wdog1 {
692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_wdog>;
694 fsl,ext-reset-output;
695};
696
697&iomuxc {
698 pinctrl_audmux: audmuxgrp {
699 fsl,pins = <
700 /* AUD4 */
701 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
702 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
703 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
704 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
705 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
706 /* AUD6 */
707 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
708 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
709 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
710 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
711 >;
712 };
713
714 pinctrl_ecspi3: escpi3grp {
715 fsl,pins = <
716 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
717 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
718 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
719 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
720 >;
721 };
722
723 pinctrl_enet: enetgrp {
724 fsl,pins = <
725 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
726 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
727 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
728 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
729 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
730 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
731 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
732 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
733 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
734 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
735 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
736 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
737 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
738 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
739 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
740 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
741 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
742 >;
743 };
744
745 pinctrl_flexcan: flexcangrp {
746 fsl,pins = <
747 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
748 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
749 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
750 >;
751 };
752
753 pinctrl_gpio_leds: gpioledsgrp {
754 fsl,pins = <
755 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
756 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
757 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
758 >;
759 };
760
761 pinctrl_i2c1: i2c1grp {
762 fsl,pins = <
763 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
764 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
765 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
766 >;
767 };
768
769 pinctrl_i2c2: i2c2grp {
770 fsl,pins = <
771 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
772 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
773 >;
774 };
775
776 pinctrl_i2c3: i2c3grp {
777 fsl,pins = <
778 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
779 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
780 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
781 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
782 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
783 >;
784 };
785
786 pinctrl_imu: imugrp {
787 fsl,pins = <
788 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
789 >;
790 };
791
792 pinctrl_keypad: keypadgrp {
793 fsl,pins = <
794 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
795 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
796 >;
797 };
798
799 pinctrl_mag: maggrp {
800 fsl,pins = <
801 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
802 >;
803 };
804
805 pinctrl_pcie: pciegrp {
806 fsl,pins = <
807 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
808 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
809 >;
810 };
811
812 pinctrl_pmic: pmicgrp {
813 fsl,pins = <
814 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
815 >;
816 };
817
818 pinctrl_pps: ppsgrp {
819 fsl,pins = <
820 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
821 >;
822 };
823
824 pinctrl_pwm2: pwm2grp {
825 fsl,pins = <
826 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
827 >;
828 };
829
830 pinctrl_pwm3: pwm3grp {
831 fsl,pins = <
832 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
833 >;
834 };
835
836 pinctrl_pwm4: pwm4grp {
837 fsl,pins = <
838 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
839 >;
840 };
841
842 pinctrl_uart1: uart1grp {
843 fsl,pins = <
844 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
845 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
846 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
847 >;
848 };
849
850 pinctrl_uart2: uart2grp {
851 fsl,pins = <
852 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
853 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
854 >;
855 };
856
857 pinctrl_uart5: uart5grp {
858 fsl,pins = <
859 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
860 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
861 >;
862 };
863
864 pinctrl_usbh1: usbh1grp {
865 fsl,pins = <
866 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
867 >;
868 };
869
870 pinctrl_usbotg: usbotggrp {
871 fsl,pins = <
872 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
873 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
874 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
875 >;
876 };
877
878 pinctrl_usdhc2: usdhc2grp {
879 fsl,pins = <
880 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
881 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
882 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
883 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
884 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
885 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
886 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
887 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
888 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
889 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
890 >;
891 };
892
893 pinctrl_usdhc3: usdhc3grp {
894 fsl,pins = <
895 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
896 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
897 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
898 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
899 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
900 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
901 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
902 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
903 >;
904 };
905
906 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
907 fsl,pins = <
908 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
909 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
910 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
911 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
912 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
913 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
914 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
915 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
916 >;
917 };
918
919 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
920 fsl,pins = <
921 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
922 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
923 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
924 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
925 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
926 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
927 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
928 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
929 >;
930 };
931
932 pinctrl_wdog: wdoggrp {
933 fsl,pins = <
934 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
935 >;
936 };
937};