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git01.mediatek.com / filogic / uboot / ce3cf6ad8775f33c5a7dba36b7b01c1a18574d8c / . / arch / arm / dts / tegra20-colibri.dts
blob: 777f63e5bdb6a6255b44aba317c8445393fc70ac [file] [log] [blame]
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]4
5/ {
6 model = "Toradex Colibri T20";
Marcel Ziswiler2ec89a82015-08-06 00:47:01 +0200[diff] [blame]7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]13 aliases {
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]17 usb0 = "/usb@c5008000";
18 usb1 = "/usb@c5000000";
19 usb2 = "/usb@c5004000";
Stephen Warrend55aadc2016-09-13 10:45:43 -0600[diff] [blame]20 mmc0 = "/sdhci@c8000600";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]34 usb@c5000000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]35 statuc = "okay";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]36 dr_mode = "otg";
37 };
38
39 usb@c5004000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]40 statuc = "okay";
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]41 /* VBUS_LAN */
Stephen Warren7c259752016-09-15 12:19:37 -0600[diff] [blame]42 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
43 GPIO_ACTIVE_LOW>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]44 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]45 };
46
47 usb@c5008000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]48 statuc = "okay";
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]49 /* USBH_PEN */
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]50 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]51 };
52
53 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]54 nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]55 nvidia,width = <8>;
56 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
57
58 nand@0 {
59 reg = <0>;
60 compatible = "nand-flash";
61 };
62 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]63
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]64 /*
65 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
66 * board)
67 */
68 i2c@7000c000 {
69 status = "okay";
70 clock-frequency = <100000>;
71 };
72
73 /* GEN2_I2C: unused */
74
75 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
76 i2c@7000c400 {
77 status = "okay";
78 clock-frequency = <100000>;
79 };
80
81 /*
82 * PWR_I2C: power I2C to PMIC and temperature sensor
83 */
84 i2c@7000d000 {
85 status = "okay";
86 clock-frequency = <100000>;
87 };
88
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]89 sdhci@c8000600 {
90 status = "okay";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]91 bus-width = <4>;
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]92 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]93 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]94
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]95 clocks {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 clk32k_in: clock@0 {
101 compatible = "fixed-clock";
102 reg=<0>;
103 #clock-cells = <0>;
104 clock-frequency = <32768>;
105 };
106 };
107
Simon Glassd8af3c92016-01-30 16:38:01 -0700[diff] [blame]108 pwm: pwm@7000a000 {
109 status = "okay";
110 };
111
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]112 lcd_panel: panel {
113 clock = <25175000>;
114 xres = <640>;
115 yres = <480>;
116 left-margin = <48>; /* horizontal back porch */
117 right-margin = <16>; /* horizontal front porch */
118 hsync-len = <96>;
119 lower-margin = <11>; /* vertical front porch */
120 upper-margin = <31>; /* vertical back porch */
121 vsync-len = <2>;
122 hsync-active-high;
123 vsync-active-high;
124 nvidia,bits-per-pixel = <16>;
125 nvidia,pwm = <&pwm 0 0>;
126 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
127 nvidia,panel-timings = <0 0 0 0>;
128 };
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]129};