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git01.mediatek.com / filogic / uboot / cde8c95e062c97c52a093ffaf6fc1c37c530ac3c / . / arch / arm / dts / zynq-cse-nand.dts
blob: f1fb15902a79d17a2cb3cae6fd468c2fc2137c83 [file] [log] [blame]
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Xilinx CSE NAND board DTS
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7/dts-v1/;
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Zynq CSE NAND Board";
13 compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
14
15 aliases {
16 serial0 = &dcc;
17 };
18
19 memory@0 {
20 device_type = "memory";
21 reg = <0x0 0x400000>;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 dcc: dcc {
29 compatible = "arm,dcc";
30 status = "disabled";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-all;
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]32 };
33
Michal Simek22d0df52024-09-13 11:28:44 +0200[diff] [blame]34 amba: axi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-all;
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges;
40
T Karthik Reddye9070c72020-04-15 04:45:02 -0600[diff] [blame]41 smcc: memory-controller@e000e000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 clock-names = "memclk", "apb_pclk";
45 clocks = <&clkc 11>, <&clkc 44>;
46 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
47 ranges;
48 reg = <0xe000e000 0x1000>;
49
50 nand0: flash@e1000000 {
51 compatible = "arm,pl353-nand-r2p1";
52 reg = <0xe1000000 0x1000000>;
53 };
54 };
55
Michal Simekc1bb21b2018-07-20 10:17:17 +0200[diff] [blame]56 slcr: slcr@f8000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-all;
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
61 reg = <0xF8000000 0x1000>;
62 ranges;
63 clkc: clkc@100 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-all;
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]65 #clock-cells = <1>;
66 compatible = "xlnx,ps7-clkc";
67 clock-output-names = "armpll", "ddrpll",
68 "iopll", "cpu_6or4x",
69 "cpu_3or2x", "cpu_2x", "cpu_1x",
70 "ddr2x", "ddr3x", "dci",
71 "lqspi", "smc", "pcap", "gem0",
72 "gem1", "fclk0", "fclk1",
73 "fclk2", "fclk3", "can0",
74 "can1", "sdio0", "sdio1",
75 "uart0", "uart1", "spi0",
76 "spi1", "dma", "usb0_aper",
77 "usb1_aper", "gem0_aper",
78 "gem1_aper", "sdio0_aper",
79 "sdio1_aper", "spi0_aper",
80 "spi1_aper", "can0_aper",
81 "can1_aper", "i2c0_aper",
82 "i2c1_aper", "uart0_aper",
83 "uart1_aper", "gpio_aper",
84 "lqspi_aper", "smc_aper",
85 "swdt", "dbg_trc", "dbg_apb";
86 reg = <0x100 0x100>;
87 };
88 };
Michal Simek34140ec2022-11-29 13:23:20 +0100[diff] [blame]89
90 scutimer: timer@f8f00600 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-all;
Michal Simek34140ec2022-11-29 13:23:20 +0100[diff] [blame]92 compatible = "arm,cortex-a9-twd-timer";
93 reg = <0xf8f00600 0x20>;
94 clock-frequency = <333333333>;
95 };
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]96 };
Siva Durga Prasad Paladugucc1ab0f2018-07-16 15:57:01 +0530[diff] [blame]97};
98
99&dcc {
100 status = "okay";
101};