| commit | c1bb21bce71fb166c0b5ac6e26579712589bae2a | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Fri Jul 20 10:17:17 2018 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Mon Aug 06 08:44:35 2018 +0200 |
| tree | 898d524ea11d5ef36bf7d6896f142b24f543d8a2 | |
| parent | bd35b562280e16a5afa52a66b0cb270795f3328e [diff] [blame] |
arm: zynq: Fix indentation for zynq-cse targets Trivial DT style fixes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 9b1dd19..1e16d7f 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -38,7 +38,7 @@ #size-cells = <1>; ranges; - slcr: slcr@f8000000 { + slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; @@ -72,7 +72,6 @@ }; }; }; - }; &dcc {