arm: zynq: Fix indentation for zynq-cse targets
Trivial DT style fixes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 9b1dd19..1e16d7f 100644
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -38,7 +38,7 @@
#size-cells = <1>;
ranges;
- slcr: slcr@f8000000 {
+ slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
@@ -72,7 +72,6 @@
};
};
};
-
};
&dcc {
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index edc8f59..9710aba 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -79,7 +79,6 @@
};
};
};
-
};
&dcc {