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git01.mediatek.com / filogic / uboot / cd87b1e4cf781a234e3fd0e76a26dbc93fe37572 / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: 73577e8cfd3730b9300e736f64686306770c2cf4 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]13
14 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]16 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]17};
18
19&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]21 timer1: timer@2400000 {
22 compatible = "ti,omap5430-timer";
23 reg = <0x0 0x2400000 0x0 0x80>;
24 ti,timer-alwon;
Vignesh Raghavendraf113fce2022-03-11 21:23:22 +0530[diff] [blame]25 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]27 };
28};
29
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]30&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]32 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]34 };
35};
36
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]37&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]39 main_i2c0_pins_default: main-i2c0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]41 pinctrl-single,pins = <
42 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
43 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
44 >;
45 };
46};
47
48&main_i2c0 {
Roger Quadrosef0371c2023-01-24 11:43:26 +0200[diff] [blame]49 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]51 pinctrl-names = "default";
52 pinctrl-0 = <&main_i2c0_pins_default>;
53 clock-frequency = <400000>;
54};
55
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]56&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]58};
59
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]60&usb0 {
61 dr_mode="peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]63};
64
65&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]67};
68
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]69&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]71};
72
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]73&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]75};
76
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]77&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]79};
80
81&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]83};
84
85&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]87 k3_sysreset: sysreset-controller {
88 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]90 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]91};
92
93&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]95};
96
97&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]99};
100
101&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]103};
104
105&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]107};
108
109&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]111};
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]112
113&cpsw3g {
114 reg = <0x0 0x8000000 0x0 0x200000>,
115 <0x0 0x43000200 0x0 0x8>;
116 reg-names = "cpsw_nuss", "mac_efuse";
117 /delete-property/ ranges;
Roger Quadros7350eb22023-01-24 11:43:27 +0200[diff] [blame]118 pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
119 &rgmii1_pins_default
120 &rgmii2_pins_default>;
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]121
122 cpsw-phy-sel@04044 {
123 compatible = "ti,am64-phy-gmii-sel";
124 reg = <0x0 0x43004044 0x0 0x8>;
125 };
126};
127
128&cpsw_port2 {
129 status = "disabled";
130};