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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: 64857b09099da9142a658c659a2ba65293f1f4b8 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]11
12 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]13 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]14 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]15};
16
17&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]18 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]19 timer1: timer@2400000 {
20 compatible = "ti,omap5430-timer";
21 reg = <0x0 0x2400000 0x0 0x80>;
22 ti,timer-alwon;
Vignesh Raghavendraf113fce2022-03-11 21:23:22 +0530[diff] [blame]23 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]24 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]25 };
26};
27
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]28&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]29 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]30 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]31 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]32 };
33};
34
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]35&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]36 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]37 main_i2c0_pins_default: main-i2c0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]38 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]39 pinctrl-single,pins = <
40 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
41 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
42 >;
43 };
44};
45
46&main_i2c0 {
Roger Quadrosef0371c2023-01-24 11:43:26 +0200[diff] [blame]47 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]48 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]49 pinctrl-names = "default";
50 pinctrl-0 = <&main_i2c0_pins_default>;
51 clock-frequency = <400000>;
52};
53
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]54&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]55 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]56};
57
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]58&usb0 {
59 dr_mode="peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]60 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]61};
62
63&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]64 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]65};
66
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]67&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]68 bootph-pre-ram;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]69};
70
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]71&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]72 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]73};
74
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]75&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]76 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]77};
78
79&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]80 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]81};
82
83&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]84 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]85 k3_sysreset: sysreset-controller {
86 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]87 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]88 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]89};
90
91&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]92 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]93};
94
95&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]96 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]97};
98
99&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]100 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]101};
102
103&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]104 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]105};
106
107&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]108 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]109};
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]110
111&cpsw3g {
112 reg = <0x0 0x8000000 0x0 0x200000>,
113 <0x0 0x43000200 0x0 0x8>;
114 reg-names = "cpsw_nuss", "mac_efuse";
115 /delete-property/ ranges;
Roger Quadros7350eb22023-01-24 11:43:27 +0200[diff] [blame]116 pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
117 &rgmii1_pins_default
118 &rgmii2_pins_default>;
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]119
120 cpsw-phy-sel@04044 {
121 compatible = "ti,am64-phy-gmii-sel";
122 reg = <0x0 0x43004044 0x0 0x8>;
123 };
124};
125
126&cpsw_port2 {
127 status = "disabled";
128};