blob: 4a2d240abbb645641931ec341798879bf2ffd4fb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek72536fd2015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
Michal Simeka8c94362023-07-10 14:35:49 +02005 * Michal Simek <michal.simek@amd.com>
Michal Simek72536fd2015-11-20 13:17:22 +01006 */
7
Simon Glass2dc9c342020-05-10 11:40:01 -06008#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Sean Andersonf081e882024-02-22 15:05:11 -050011#include <semihosting.h>
Michal Simek72536fd2015-11-20 13:17:22 +010012#include <spl.h>
Simon Glassdbd79542020-05-10 11:40:11 -060013#include <linux/delay.h>
Michal Simek72536fd2015-11-20 13:17:22 +010014
15#include <asm/io.h>
16#include <asm/spl.h>
17#include <asm/arch/hardware.h>
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020018#include <asm/arch/ecc_spl_init.h>
Michal Simekef955012019-12-03 15:02:50 +010019#include <asm/arch/psu_init_gpl.h>
Michal Simek72536fd2015-11-20 13:17:22 +010020#include <asm/arch/sys_proto.h>
21
Michal Simeke5710e32022-02-17 14:28:42 +010022#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
23void board_debug_uart_init(void)
24{
25 psu_uboot_init();
26}
27#endif
28
Michal Simek72536fd2015-11-20 13:17:22 +010029void board_init_f(ulong dummy)
30{
Michal Simeke5710e32022-02-17 14:28:42 +010031#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
32 psu_uboot_init();
33#endif
34
Michal Simek72536fd2015-11-20 13:17:22 +010035 board_early_init_r();
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020036#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
37 zynqmp_ecc_init();
38#endif
Michal Simek72536fd2015-11-20 13:17:22 +010039}
40
Michal Simek3eb32de2016-08-15 09:41:36 +020041static void ps_mode_reset(ulong mode)
42{
Michal Simek3eb32de2016-08-15 09:41:36 +020043 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
44 &crlapb_base->boot_pin_ctrl);
45 udelay(5);
46 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
47 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
48 &crlapb_base->boot_pin_ctrl);
49}
50
51/*
52 * Set default PS_MODE1 which is used for USB ULPI phy reset
53 * Also other resets can be connected to this certain pin
54 */
55#ifndef MODE_RESET
56# define MODE_RESET PS_MODE1
57#endif
58
Lukas Funkebae556542024-03-27 13:11:53 +010059#ifdef CONFIG_SPL_SOC_INIT
60void spl_soc_init(void)
Michal Simek72536fd2015-11-20 13:17:22 +010061{
62 preloader_console_init();
Michal Simek3eb32de2016-08-15 09:41:36 +020063 ps_mode_reset(MODE_RESET);
Michal Simek72536fd2015-11-20 13:17:22 +010064 board_init();
Michal Simekef955012019-12-03 15:02:50 +010065 psu_post_config_data();
Michal Simek72536fd2015-11-20 13:17:22 +010066}
67#endif
68
Sean Andersonf081e882024-02-22 15:05:11 -050069static u32 jtag_boot_device(void)
70{
71 return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
72}
73
Michal Simek6d651d92019-12-09 13:00:57 +010074void board_boot_order(u32 *spl_boot_list)
75{
76 spl_boot_list[0] = spl_boot_device();
77
78 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
79 spl_boot_list[1] = BOOT_DEVICE_MMC2;
80 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
81 spl_boot_list[1] = BOOT_DEVICE_MMC1;
Michal Simek2642eb72020-03-11 15:00:51 +010082
Sean Andersonf081e882024-02-22 15:05:11 -050083 spl_boot_list[2] = jtag_boot_device();
Michal Simek6d651d92019-12-09 13:00:57 +010084}
85
Michal Simek72536fd2015-11-20 13:17:22 +010086u32 spl_boot_device(void)
87{
88 u32 reg = 0;
89 u8 bootmode;
90
Michal Simek94ddcaa2016-08-30 16:17:27 +020091#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
92 /* Change default boot mode at run-time */
Michal Simeke7774b52024-03-20 12:18:35 +010093 reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE;
Michal Simek833e0c42016-10-25 11:43:02 +020094 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek94ddcaa2016-08-30 16:17:27 +020095 &crlapb_base->boot_mode);
Michal Simeke7774b52024-03-20 12:18:35 +010096#else
Michal Simek72536fd2015-11-20 13:17:22 +010097 reg = readl(&crlapb_base->boot_mode);
Michal Simek833e0c42016-10-25 11:43:02 +020098 if (reg >> BOOT_MODE_ALT_SHIFT)
99 reg >>= BOOT_MODE_ALT_SHIFT;
Michal Simeke7774b52024-03-20 12:18:35 +0100100#endif
Michal Simek833e0c42016-10-25 11:43:02 +0200101
Michal Simek72536fd2015-11-20 13:17:22 +0100102 bootmode = reg & BOOT_MODES_MASK;
103
104 switch (bootmode) {
105 case JTAG_MODE:
Sean Andersonf081e882024-02-22 15:05:11 -0500106 return jtag_boot_device();
Simon Glassb58bfe02021-08-08 12:20:09 -0600107#ifdef CONFIG_SPL_MMC
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400108 case SD_MODE1:
Michal Simeka8896202017-03-02 11:02:55 +0100109 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400110 return BOOT_DEVICE_MMC2;
Michal Simek72536fd2015-11-20 13:17:22 +0100111 case SD_MODE:
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400112 case EMMC_MODE:
Michal Simek72536fd2015-11-20 13:17:22 +0100113 return BOOT_DEVICE_MMC1;
114#endif
Andrew F. Davis6d932e62019-01-17 13:43:02 -0600115#ifdef CONFIG_SPL_DFU
Michal Simek12398ea2016-08-19 14:14:52 +0200116 case USB_MODE:
117 return BOOT_DEVICE_DFU;
118#endif
Simon Glass081a45a2021-08-08 12:20:17 -0600119#ifdef CONFIG_SPL_SATA
Michal Simek2740d372016-10-26 09:24:32 +0200120 case SW_SATA_MODE:
121 return BOOT_DEVICE_SATA;
122#endif
Simon Glassa5820472021-08-08 12:20:14 -0600123#ifdef CONFIG_SPL_SPI
Michal Simek1b19a6f2017-11-02 09:15:05 +0100124 case QSPI_MODE_24BIT:
125 case QSPI_MODE_32BIT:
126 return BOOT_DEVICE_SPI;
127#endif
Michal Simek72536fd2015-11-20 13:17:22 +0100128 default:
129 printf("Invalid Boot Mode:0x%x\n", bootmode);
130 break;
131 }
132
133 return 0;
134}
135
Michal Simek72536fd2015-11-20 13:17:22 +0100136#ifdef CONFIG_SPL_OS_BOOT
137int spl_start_uboot(void)
138{
Michal Simek72536fd2015-11-20 13:17:22 +0100139 return 0;
140}
141#endif