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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek72536fd2015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
Michal Simeka8c94362023-07-10 14:35:49 +02005 * Michal Simek <michal.simek@amd.com>
Michal Simek72536fd2015-11-20 13:17:22 +01006 */
7
8#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Sean Andersonf081e882024-02-22 15:05:11 -050012#include <semihosting.h>
Michal Simek72536fd2015-11-20 13:17:22 +010013#include <spl.h>
Simon Glassdbd79542020-05-10 11:40:11 -060014#include <linux/delay.h>
Michal Simek72536fd2015-11-20 13:17:22 +010015
16#include <asm/io.h>
17#include <asm/spl.h>
18#include <asm/arch/hardware.h>
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020019#include <asm/arch/ecc_spl_init.h>
Michal Simekef955012019-12-03 15:02:50 +010020#include <asm/arch/psu_init_gpl.h>
Michal Simek72536fd2015-11-20 13:17:22 +010021#include <asm/arch/sys_proto.h>
22
Michal Simeke5710e32022-02-17 14:28:42 +010023#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
24void board_debug_uart_init(void)
25{
26 psu_uboot_init();
27}
28#endif
29
Michal Simek72536fd2015-11-20 13:17:22 +010030void board_init_f(ulong dummy)
31{
Michal Simeke5710e32022-02-17 14:28:42 +010032#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
33 psu_uboot_init();
34#endif
35
Michal Simek72536fd2015-11-20 13:17:22 +010036 board_early_init_r();
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020037#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
38 zynqmp_ecc_init();
39#endif
Michal Simek72536fd2015-11-20 13:17:22 +010040}
41
Michal Simek3eb32de2016-08-15 09:41:36 +020042static void ps_mode_reset(ulong mode)
43{
Michal Simek3eb32de2016-08-15 09:41:36 +020044 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
45 &crlapb_base->boot_pin_ctrl);
46 udelay(5);
47 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
48 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
49 &crlapb_base->boot_pin_ctrl);
50}
51
52/*
53 * Set default PS_MODE1 which is used for USB ULPI phy reset
54 * Also other resets can be connected to this certain pin
55 */
56#ifndef MODE_RESET
57# define MODE_RESET PS_MODE1
58#endif
59
Michal Simek72536fd2015-11-20 13:17:22 +010060#ifdef CONFIG_SPL_BOARD_INIT
61void spl_board_init(void)
62{
63 preloader_console_init();
Michal Simek3eb32de2016-08-15 09:41:36 +020064 ps_mode_reset(MODE_RESET);
Michal Simek72536fd2015-11-20 13:17:22 +010065 board_init();
Michal Simekef955012019-12-03 15:02:50 +010066 psu_post_config_data();
Michal Simek72536fd2015-11-20 13:17:22 +010067}
68#endif
69
Sean Andersonf081e882024-02-22 15:05:11 -050070static u32 jtag_boot_device(void)
71{
72 return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
73}
74
Michal Simek6d651d92019-12-09 13:00:57 +010075void board_boot_order(u32 *spl_boot_list)
76{
77 spl_boot_list[0] = spl_boot_device();
78
79 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
80 spl_boot_list[1] = BOOT_DEVICE_MMC2;
81 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
82 spl_boot_list[1] = BOOT_DEVICE_MMC1;
Michal Simek2642eb72020-03-11 15:00:51 +010083
Sean Andersonf081e882024-02-22 15:05:11 -050084 spl_boot_list[2] = jtag_boot_device();
Michal Simek6d651d92019-12-09 13:00:57 +010085}
86
Michal Simek72536fd2015-11-20 13:17:22 +010087u32 spl_boot_device(void)
88{
89 u32 reg = 0;
90 u8 bootmode;
91
Michal Simek94ddcaa2016-08-30 16:17:27 +020092#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
93 /* Change default boot mode at run-time */
Michal Simeke7774b52024-03-20 12:18:35 +010094 reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE;
Michal Simek833e0c42016-10-25 11:43:02 +020095 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek94ddcaa2016-08-30 16:17:27 +020096 &crlapb_base->boot_mode);
Michal Simeke7774b52024-03-20 12:18:35 +010097#else
Michal Simek72536fd2015-11-20 13:17:22 +010098 reg = readl(&crlapb_base->boot_mode);
Michal Simek833e0c42016-10-25 11:43:02 +020099 if (reg >> BOOT_MODE_ALT_SHIFT)
100 reg >>= BOOT_MODE_ALT_SHIFT;
Michal Simeke7774b52024-03-20 12:18:35 +0100101#endif
Michal Simek833e0c42016-10-25 11:43:02 +0200102
Michal Simek72536fd2015-11-20 13:17:22 +0100103 bootmode = reg & BOOT_MODES_MASK;
104
105 switch (bootmode) {
106 case JTAG_MODE:
Sean Andersonf081e882024-02-22 15:05:11 -0500107 return jtag_boot_device();
Simon Glassb58bfe02021-08-08 12:20:09 -0600108#ifdef CONFIG_SPL_MMC
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400109 case SD_MODE1:
Michal Simeka8896202017-03-02 11:02:55 +0100110 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400111 return BOOT_DEVICE_MMC2;
Michal Simek72536fd2015-11-20 13:17:22 +0100112 case SD_MODE:
Jean-Francois Dagenais865778a2017-04-02 21:44:34 -0400113 case EMMC_MODE:
Michal Simek72536fd2015-11-20 13:17:22 +0100114 return BOOT_DEVICE_MMC1;
115#endif
Andrew F. Davis6d932e62019-01-17 13:43:02 -0600116#ifdef CONFIG_SPL_DFU
Michal Simek12398ea2016-08-19 14:14:52 +0200117 case USB_MODE:
118 return BOOT_DEVICE_DFU;
119#endif
Simon Glass081a45a2021-08-08 12:20:17 -0600120#ifdef CONFIG_SPL_SATA
Michal Simek2740d372016-10-26 09:24:32 +0200121 case SW_SATA_MODE:
122 return BOOT_DEVICE_SATA;
123#endif
Simon Glassa5820472021-08-08 12:20:14 -0600124#ifdef CONFIG_SPL_SPI
Michal Simek1b19a6f2017-11-02 09:15:05 +0100125 case QSPI_MODE_24BIT:
126 case QSPI_MODE_32BIT:
127 return BOOT_DEVICE_SPI;
128#endif
Michal Simek72536fd2015-11-20 13:17:22 +0100129 default:
130 printf("Invalid Boot Mode:0x%x\n", bootmode);
131 break;
132 }
133
134 return 0;
135}
136
Michal Simek72536fd2015-11-20 13:17:22 +0100137#ifdef CONFIG_SPL_OS_BOOT
138int spl_start_uboot(void)
139{
Michal Simek72536fd2015-11-20 13:17:22 +0100140 return 0;
141}
142#endif