blob: 9fff1bc1a10396660f51205633d37c1f0b327026 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutfd83e762018-04-13 23:51:33 +02002/*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasutfd83e762018-04-13 23:51:33 +02005 */
6
Marek Vasutfd83e762018-04-13 23:51:33 +02007#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -07008#include <cpu_func.h>
Marek Vasutfd83e762018-04-13 23:51:33 +02009#include <fdtdec.h>
10#include <mmc.h>
11#include <dm.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070013#include <dm/device_compat.h>
Marek Vasutfd83e762018-04-13 23:51:33 +020014#include <dm/pinctrl.h>
15#include <linux/compat.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Masahiro Yamada6373a172020-02-14 16:40:19 +090017#include <linux/dma-mapping.h>
Marek Vasutfd83e762018-04-13 23:51:33 +020018#include <linux/io.h>
19#include <linux/sizes.h>
20#include <power/regulator.h>
21#include <asm/unaligned.h>
22
23#include "tmio-common.h"
24
25DECLARE_GLOBAL_DATA_PTR;
26
27static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
28{
29 return readq(priv->regbase + (reg << 1));
30}
31
32static void tmio_sd_writeq(struct tmio_sd_priv *priv,
33 u64 val, unsigned int reg)
34{
35 writeq(val, priv->regbase + (reg << 1));
36}
37
38static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
39{
40 return readw(priv->regbase + (reg >> 1));
41}
42
43static void tmio_sd_writew(struct tmio_sd_priv *priv,
44 u16 val, unsigned int reg)
45{
46 writew(val, priv->regbase + (reg >> 1));
47}
48
49u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
50{
51 u32 val;
52
53 if (priv->caps & TMIO_SD_CAP_64BIT)
54 return readl(priv->regbase + (reg << 1));
55 else if (priv->caps & TMIO_SD_CAP_16BIT) {
56 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
57 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
58 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
59 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
60 }
61 return val;
62 } else
63 return readl(priv->regbase + reg);
64}
65
66void tmio_sd_writel(struct tmio_sd_priv *priv,
67 u32 val, unsigned int reg)
68{
69 if (priv->caps & TMIO_SD_CAP_64BIT)
70 writel(val, priv->regbase + (reg << 1));
71 else if (priv->caps & TMIO_SD_CAP_16BIT) {
72 writew(val & 0xffff, priv->regbase + (reg >> 1));
73 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
74 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
75 reg == TMIO_SD_ARG)
76 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
77 } else
78 writel(val, priv->regbase + reg);
79}
80
Marek Vasutdc86e912018-10-30 22:05:54 +010081static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
Marek Vasutfd83e762018-04-13 23:51:33 +020082{
83 struct tmio_sd_priv *priv = dev_get_priv(dev);
84 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
85
86 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
87 /*
88 * TIMEOUT must be returned for unsupported command. Do not
89 * display error log since this might be a part of sequence to
90 * distinguish between SD and MMC.
91 */
92 return -ETIMEDOUT;
93 }
94
95 if (info2 & TMIO_SD_INFO2_ERR_TO) {
96 dev_err(dev, "timeout error\n");
97 return -ETIMEDOUT;
98 }
99
100 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
101 TMIO_SD_INFO2_ERR_IDX)) {
Marek Vasutdc86e912018-10-30 22:05:54 +0100102 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
103 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
104 dev_err(dev, "communication out of sync\n");
Marek Vasutfd83e762018-04-13 23:51:33 +0200105 return -EILSEQ;
106 }
107
108 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
109 TMIO_SD_INFO2_ERR_ILW)) {
110 dev_err(dev, "illegal access\n");
111 return -EIO;
112 }
113
114 return 0;
115}
116
Marek Vasutdc86e912018-10-30 22:05:54 +0100117static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
118 unsigned int reg, u32 flag)
Marek Vasutfd83e762018-04-13 23:51:33 +0200119{
120 struct tmio_sd_priv *priv = dev_get_priv(dev);
121 long wait = 1000000;
122 int ret;
123
Marek Vasutf0ea8a72023-10-14 23:56:03 +0200124 while (true) {
125 if (tmio_sd_readl(priv, reg) & flag)
126 return tmio_sd_check_error(dev, cmd);
127
Marek Vasutfd83e762018-04-13 23:51:33 +0200128 if (wait-- < 0) {
129 dev_err(dev, "timeout\n");
130 return -ETIMEDOUT;
131 }
132
Marek Vasutdc86e912018-10-30 22:05:54 +0100133 ret = tmio_sd_check_error(dev, cmd);
Marek Vasutfd83e762018-04-13 23:51:33 +0200134 if (ret)
135 return ret;
136
137 udelay(1);
138 }
139
140 return 0;
141}
142
143#define tmio_pio_read_fifo(__width, __suffix) \
144static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
145 char *pbuf, uint blksz) \
146{ \
147 u##__width *buf = (u##__width *)pbuf; \
148 int i; \
149 \
150 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
151 for (i = 0; i < blksz / ((__width) / 8); i++) { \
152 *buf++ = tmio_sd_read##__suffix(priv, \
153 TMIO_SD_BUF); \
154 } \
155 } else { \
156 for (i = 0; i < blksz / ((__width) / 8); i++) { \
157 u##__width data; \
158 data = tmio_sd_read##__suffix(priv, \
159 TMIO_SD_BUF); \
160 put_unaligned(data, buf++); \
161 } \
162 } \
163}
164
165tmio_pio_read_fifo(64, q)
166tmio_pio_read_fifo(32, l)
167tmio_pio_read_fifo(16, w)
168
Marek Vasutdc86e912018-10-30 22:05:54 +0100169static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
170 char *pbuf, uint blocksize)
Marek Vasutfd83e762018-04-13 23:51:33 +0200171{
172 struct tmio_sd_priv *priv = dev_get_priv(dev);
173 int ret;
174
175 /* wait until the buffer is filled with data */
Marek Vasutdc86e912018-10-30 22:05:54 +0100176 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
177 TMIO_SD_INFO2_BRE);
Marek Vasutfd83e762018-04-13 23:51:33 +0200178 if (ret)
179 return ret;
180
181 /*
182 * Clear the status flag _before_ read the buffer out because
183 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
184 */
185 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
186
187 if (priv->caps & TMIO_SD_CAP_64BIT)
188 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
189 else if (priv->caps & TMIO_SD_CAP_16BIT)
190 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
191 else
192 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
193
194 return 0;
195}
196
197#define tmio_pio_write_fifo(__width, __suffix) \
198static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
199 const char *pbuf, uint blksz)\
200{ \
201 const u##__width *buf = (const u##__width *)pbuf; \
202 int i; \
203 \
204 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
205 for (i = 0; i < blksz / ((__width) / 8); i++) { \
206 tmio_sd_write##__suffix(priv, *buf++, \
207 TMIO_SD_BUF); \
208 } \
209 } else { \
210 for (i = 0; i < blksz / ((__width) / 8); i++) { \
211 u##__width data = get_unaligned(buf++); \
212 tmio_sd_write##__suffix(priv, data, \
213 TMIO_SD_BUF); \
214 } \
215 } \
216}
217
218tmio_pio_write_fifo(64, q)
219tmio_pio_write_fifo(32, l)
220tmio_pio_write_fifo(16, w)
221
Marek Vasutdc86e912018-10-30 22:05:54 +0100222static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
Marek Vasutfd83e762018-04-13 23:51:33 +0200223 const char *pbuf, uint blocksize)
224{
225 struct tmio_sd_priv *priv = dev_get_priv(dev);
226 int ret;
227
228 /* wait until the buffer becomes empty */
Marek Vasutdc86e912018-10-30 22:05:54 +0100229 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
230 TMIO_SD_INFO2_BWE);
Marek Vasutfd83e762018-04-13 23:51:33 +0200231 if (ret)
232 return ret;
233
234 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
235
236 if (priv->caps & TMIO_SD_CAP_64BIT)
237 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
238 else if (priv->caps & TMIO_SD_CAP_16BIT)
239 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
240 else
241 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
242
243 return 0;
244}
245
Marek Vasutdc86e912018-10-30 22:05:54 +0100246static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
247 struct mmc_data *data)
Marek Vasutfd83e762018-04-13 23:51:33 +0200248{
249 const char *src = data->src;
250 char *dest = data->dest;
251 int i, ret;
252
253 for (i = 0; i < data->blocks; i++) {
254 if (data->flags & MMC_DATA_READ)
Marek Vasutdc86e912018-10-30 22:05:54 +0100255 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
Marek Vasutfd83e762018-04-13 23:51:33 +0200256 data->blocksize);
257 else
Marek Vasutdc86e912018-10-30 22:05:54 +0100258 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
Marek Vasutfd83e762018-04-13 23:51:33 +0200259 data->blocksize);
260 if (ret)
261 return ret;
262
263 if (data->flags & MMC_DATA_READ)
264 dest += data->blocksize;
265 else
266 src += data->blocksize;
267 }
268
269 return 0;
270}
271
272static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
273 dma_addr_t dma_addr)
274{
275 u32 tmp;
276
277 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
278 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
279
280 /* enable DMA */
281 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
282 tmp |= TMIO_SD_EXTMODE_DMA_EN;
283 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
284
285 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
286
287 /* suppress the warning "right shift count >= width of type" */
288 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
289
290 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
291
292 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
293}
294
295static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
296 unsigned int blocks)
297{
298 struct tmio_sd_priv *priv = dev_get_priv(dev);
299 long wait = 1000000 + 10 * blocks;
300
Marek Vasutc2275a32024-02-20 09:38:14 +0100301 for (;;) {
302 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)
303 break;
304
305 if (tmio_sd_readl(priv, TMIO_SD_INFO1) & TMIO_SD_INFO1_CMP)
306 break;
307
Marek Vasutfd83e762018-04-13 23:51:33 +0200308 if (wait-- < 0) {
309 dev_err(dev, "timeout during DMA\n");
310 return -ETIMEDOUT;
311 }
312
313 udelay(10);
314 }
315
316 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
317 dev_err(dev, "error during DMA\n");
318 return -EIO;
319 }
320
321 return 0;
322}
323
324static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
325{
326 struct tmio_sd_priv *priv = dev_get_priv(dev);
327 size_t len = data->blocks * data->blocksize;
328 void *buf;
329 enum dma_data_direction dir;
330 dma_addr_t dma_addr;
331 u32 poll_flag, tmp;
332 int ret;
333
334 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
335
Marek Vasutd6e2f872021-01-03 11:38:25 +0100336 tmp |= priv->idma_bus_width;
337
Marek Vasutfd83e762018-04-13 23:51:33 +0200338 if (data->flags & MMC_DATA_READ) {
339 buf = data->dest;
340 dir = DMA_FROM_DEVICE;
341 /*
342 * The DMA READ completion flag position differs on Socionext
343 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
Marek Vasute9a28222019-01-11 23:45:54 +0100344 * bit 17 is a hardware bug and forbidden. It is either bit 17
345 * or bit 20 on Renesas SoCs, depending on SoC.
Marek Vasutfd83e762018-04-13 23:51:33 +0200346 */
Marek Vasute9a28222019-01-11 23:45:54 +0100347 poll_flag = priv->read_poll_flag;
Marek Vasutfd83e762018-04-13 23:51:33 +0200348 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
349 } else {
350 buf = (void *)data->src;
351 dir = DMA_TO_DEVICE;
352 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
353 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
354 }
355
356 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
357
Vignesh Raghavendra0892e712020-01-16 14:23:46 +0530358 dma_addr = dma_map_single(buf, len, dir);
Marek Vasutfd83e762018-04-13 23:51:33 +0200359
360 tmio_sd_dma_start(priv, dma_addr);
361
362 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
363
Marek Vasut314b9ca2019-01-11 23:38:07 +0100364 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
365 udelay(1);
366
Masahiro Yamada05a5dba2020-02-14 16:40:18 +0900367 dma_unmap_single(dma_addr, len, dir);
Marek Vasutfd83e762018-04-13 23:51:33 +0200368
369 return ret;
370}
371
372/* check if the address is DMA'able */
Hiroyuki Yokoyamaed5aa492020-03-07 17:32:59 +0100373static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
Marek Vasutfd83e762018-04-13 23:51:33 +0200374{
Hiroyuki Yokoyamaed5aa492020-03-07 17:32:59 +0100375 uintptr_t addr = (uintptr_t)data->src;
Marek Vasutc7da6e342018-10-03 00:44:37 +0200376
Marek Vasutfd83e762018-04-13 23:51:33 +0200377 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
378 return false;
379
Hai Pham206dc912023-02-28 22:24:06 +0100380 if (IS_ENABLED(CONFIG_RCAR_64)) {
Marek Vasutd4be38e2023-02-28 22:18:13 +0100381 if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
382 return false;
383 /* Gen3 DMA has 32bit limit */
384 if (sizeof(addr) > 4 && addr >> 32)
385 return false;
386 }
Marek Vasut967db0e2018-10-03 00:46:24 +0200387
Simon Glass7ec24132024-09-29 19:49:48 -0600388#ifdef CONFIG_XPL_BUILD
Marek Vasutc738e0c2023-04-08 19:35:37 +0200389 if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !IS_ENABLED(CONFIG_ARM64)) {
Marek Vasutd4be38e2023-02-28 22:18:13 +0100390 /*
391 * For UniPhier ARMv7 SoCs, the stack is allocated in locked
392 * ways of L2, which is unreachable from the DMA engine.
393 */
394 if (addr < CONFIG_SPL_STACK)
395 return false;
396 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200397#endif
398
399 return true;
400}
401
402int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
403 struct mmc_data *data)
404{
405 struct tmio_sd_priv *priv = dev_get_priv(dev);
406 int ret;
407 u32 tmp;
408
409 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
410 dev_err(dev, "command busy\n");
411 return -EBUSY;
412 }
413
414 /* clear all status flags */
415 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
416 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
417
418 /* disable DMA once */
419 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
420 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
421 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
422
423 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
424
425 tmp = cmd->cmdidx;
426
427 if (data) {
428 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
429 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
430
431 /* Do not send CMD12 automatically */
432 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
433
434 if (data->blocks > 1)
435 tmp |= TMIO_SD_CMD_MULTI;
436
437 if (data->flags & MMC_DATA_READ)
438 tmp |= TMIO_SD_CMD_RD;
439 }
440
441 /*
442 * Do not use the response type auto-detection on this hardware.
443 * CMD8, for example, has different response types on SD and eMMC,
444 * while this controller always assumes the response type for SD.
445 * Set the response type manually.
446 */
447 switch (cmd->resp_type) {
448 case MMC_RSP_NONE:
449 tmp |= TMIO_SD_CMD_RSP_NONE;
450 break;
451 case MMC_RSP_R1:
452 tmp |= TMIO_SD_CMD_RSP_R1;
453 break;
454 case MMC_RSP_R1b:
455 tmp |= TMIO_SD_CMD_RSP_R1B;
456 break;
457 case MMC_RSP_R2:
458 tmp |= TMIO_SD_CMD_RSP_R2;
459 break;
460 case MMC_RSP_R3:
461 tmp |= TMIO_SD_CMD_RSP_R3;
462 break;
463 default:
464 dev_err(dev, "unknown response type\n");
465 return -EINVAL;
466 }
467
468 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
469 cmd->cmdidx, tmp, cmd->cmdarg);
470 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
471
Marek Vasutdc86e912018-10-30 22:05:54 +0100472 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
473 TMIO_SD_INFO1_RSP);
Marek Vasutfd83e762018-04-13 23:51:33 +0200474 if (ret)
475 return ret;
476
477 if (cmd->resp_type & MMC_RSP_136) {
478 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
479 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
480 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
481 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
482
483 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
484 ((rsp_103_72 & 0xff000000) >> 24);
485 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
486 ((rsp_71_40 & 0xff000000) >> 24);
487 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
488 ((rsp_39_8 & 0xff000000) >> 24);
489 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
490 } else {
491 /* bit 39-8 */
492 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
493 }
494
495 if (data) {
496 /* use DMA if the HW supports it and the buffer is aligned */
497 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
Hiroyuki Yokoyamaed5aa492020-03-07 17:32:59 +0100498 tmio_sd_addr_is_dmaable(data))
Marek Vasutfd83e762018-04-13 23:51:33 +0200499 ret = tmio_sd_dma_xfer(dev, data);
500 else
Marek Vasutdc86e912018-10-30 22:05:54 +0100501 ret = tmio_sd_pio_xfer(dev, cmd, data);
Marek Vasut6b4a8ba2018-10-30 21:53:29 +0100502 if (ret)
503 return ret;
Marek Vasutfd83e762018-04-13 23:51:33 +0200504
Marek Vasutdc86e912018-10-30 22:05:54 +0100505 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
506 TMIO_SD_INFO1_CMP);
Marek Vasutfd83e762018-04-13 23:51:33 +0200507 if (ret)
508 return ret;
509 }
510
Marek Vasutdc86e912018-10-30 22:05:54 +0100511 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
Marek Vasut6b4a8ba2018-10-30 21:53:29 +0100512 TMIO_SD_INFO2_SCLKDIVEN);
Marek Vasutfd83e762018-04-13 23:51:33 +0200513}
514
515static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
516 struct mmc *mmc)
517{
518 u32 val, tmp;
519
520 switch (mmc->bus_width) {
521 case 0:
522 case 1:
523 val = TMIO_SD_OPTION_WIDTH_1;
524 break;
525 case 4:
526 val = TMIO_SD_OPTION_WIDTH_4;
527 break;
528 case 8:
529 val = TMIO_SD_OPTION_WIDTH_8;
530 break;
531 default:
532 return -EINVAL;
533 }
534
535 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
536 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
537 tmp |= val;
538 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
539
540 return 0;
541}
542
543static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
544 struct mmc *mmc)
545{
546 u32 tmp;
547
548 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
549 if (mmc->ddr_mode)
550 tmp |= TMIO_SD_IF_MODE_DDR;
551 else
552 tmp &= ~TMIO_SD_IF_MODE_DDR;
553 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
554}
555
Marek Vasutda90a1b2018-06-13 08:02:55 +0200556static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
557{
558 return priv->clk_get_rate(priv);
559}
560
Marek Vasut9763b182018-11-15 22:01:33 +0100561static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
Marek Vasutfd83e762018-04-13 23:51:33 +0200562{
563 unsigned int divisor;
Marek Vasut9763b182018-11-15 22:01:33 +0100564 u32 tmp, val = 0;
Marek Vasutda90a1b2018-06-13 08:02:55 +0200565 ulong mclk;
Marek Vasutfd83e762018-04-13 23:51:33 +0200566
Marek Vasut9763b182018-11-15 22:01:33 +0100567 if (mmc->clock) {
568 mclk = tmio_sd_clk_get_rate(priv);
Marek Vasutfd83e762018-04-13 23:51:33 +0200569
Marek Vasut9763b182018-11-15 22:01:33 +0100570 divisor = DIV_ROUND_UP(mclk, mmc->clock);
Marek Vasutda90a1b2018-06-13 08:02:55 +0200571
Marek Vasut9763b182018-11-15 22:01:33 +0100572 /* Do not set divider to 0xff in DDR mode */
573 if (mmc->ddr_mode && (divisor == 1))
574 divisor = 2;
Marek Vasutfd83e762018-04-13 23:51:33 +0200575
Marek Vasut9763b182018-11-15 22:01:33 +0100576 if (divisor <= 1)
577 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
578 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
579 else if (divisor <= 2)
580 val = TMIO_SD_CLKCTL_DIV2;
581 else if (divisor <= 4)
582 val = TMIO_SD_CLKCTL_DIV4;
583 else if (divisor <= 8)
584 val = TMIO_SD_CLKCTL_DIV8;
585 else if (divisor <= 16)
586 val = TMIO_SD_CLKCTL_DIV16;
587 else if (divisor <= 32)
588 val = TMIO_SD_CLKCTL_DIV32;
589 else if (divisor <= 64)
590 val = TMIO_SD_CLKCTL_DIV64;
591 else if (divisor <= 128)
592 val = TMIO_SD_CLKCTL_DIV128;
593 else if (divisor <= 256)
594 val = TMIO_SD_CLKCTL_DIV256;
595 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
596 val = TMIO_SD_CLKCTL_DIV512;
597 else
598 val = TMIO_SD_CLKCTL_DIV1024;
599 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200600
601 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
Marek Vasut9763b182018-11-15 22:01:33 +0100602 if (mmc->clock &&
603 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
604 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
605 /*
606 * Stop the clock before changing its rate
607 * to avoid a glitch signal
608 */
609 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
610 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
Marek Vasutfd83e762018-04-13 23:51:33 +0200611
Marek Vasut9763b182018-11-15 22:01:33 +0100612 /* Change the clock rate. */
613 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
614 tmp |= val;
615 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200616
Marek Vasut9763b182018-11-15 22:01:33 +0100617 /* Enable or Disable the clock */
618 if (mmc->clk_disable) {
Marek Vasut5abfb132018-06-13 08:02:55 +0200619 tmp |= TMIO_SD_CLKCTL_OFFEN;
620 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
Marek Vasut9763b182018-11-15 22:01:33 +0100621 } else {
622 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
623 tmp |= TMIO_SD_CLKCTL_SCLKEN;
Marek Vasut5abfb132018-06-13 08:02:55 +0200624 }
Marek Vasut9763b182018-11-15 22:01:33 +0100625
Marek Vasutfd83e762018-04-13 23:51:33 +0200626 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
627
628 udelay(1000);
629}
630
631static void tmio_sd_set_pins(struct udevice *dev)
632{
633 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
Marek Vasutfd83e762018-04-13 23:51:33 +0200634 struct tmio_sd_priv *priv = dev_get_priv(dev);
635
Marek Vasutd4be38e2023-02-28 22:18:13 +0100636 if (CONFIG_IS_ENABLED(DM_REGULATOR) && priv->vqmmc_dev) {
Marek Vasutfd83e762018-04-13 23:51:33 +0200637 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
638 regulator_set_value(priv->vqmmc_dev, 1800000);
639 else
640 regulator_set_value(priv->vqmmc_dev, 3300000);
641 regulator_set_enable(priv->vqmmc_dev, true);
642 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200643
Marek Vasutd4be38e2023-02-28 22:18:13 +0100644 if (CONFIG_IS_ENABLED(PINCTRL)) {
645 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
646 pinctrl_select_state(dev, "state_uhs");
647 else
648 pinctrl_select_state(dev, "default");
649 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200650}
651
652int tmio_sd_set_ios(struct udevice *dev)
653{
654 struct tmio_sd_priv *priv = dev_get_priv(dev);
655 struct mmc *mmc = mmc_get_mmc_dev(dev);
656 int ret;
657
658 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
659 mmc->clock, mmc->ddr_mode, mmc->bus_width);
660
Marek Vasutbfe04e02018-06-13 08:02:55 +0200661 tmio_sd_set_clk_rate(priv, mmc);
Marek Vasutfd83e762018-04-13 23:51:33 +0200662 ret = tmio_sd_set_bus_width(priv, mmc);
663 if (ret)
664 return ret;
665 tmio_sd_set_ddr_mode(priv, mmc);
Marek Vasutfd83e762018-04-13 23:51:33 +0200666 tmio_sd_set_pins(dev);
667
668 return 0;
669}
670
671int tmio_sd_get_cd(struct udevice *dev)
672{
673 struct tmio_sd_priv *priv = dev_get_priv(dev);
674
675 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
676 return 1;
677
678 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
679 TMIO_SD_INFO1_CD);
680}
681
682static void tmio_sd_host_init(struct tmio_sd_priv *priv)
683{
684 u32 tmp;
685
686 /* soft reset of the host */
687 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
688 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
689 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
690 tmp |= TMIO_SD_SOFT_RST_RSTX;
691 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
692
693 /* FIXME: implement eMMC hw_reset */
694
695 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
696
697 /*
698 * Connected to 32bit AXI.
699 * This register dropped backward compatibility at version 0x10.
700 * Write an appropriate value depending on the IP version.
701 */
Marek Vasut2a43f882019-02-14 15:16:24 +0100702 if (priv->version >= 0x10) {
703 if (priv->caps & TMIO_SD_CAP_64BIT)
Marek Vasut1a4abf52019-02-19 19:20:14 +0100704 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
Marek Vasut2a43f882019-02-14 15:16:24 +0100705 else
706 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
707 } else {
Marek Vasutfd83e762018-04-13 23:51:33 +0200708 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
Marek Vasut2a43f882019-02-14 15:16:24 +0100709 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200710
711 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
712 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
713 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
Marek Vasutd6e2f872021-01-03 11:38:25 +0100714 tmp |= priv->idma_bus_width;
Marek Vasutfd83e762018-04-13 23:51:33 +0200715 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
716 }
717}
718
719int tmio_sd_bind(struct udevice *dev)
720{
Simon Glassfa20e932020-12-03 16:55:20 -0700721 struct tmio_sd_plat *plat = dev_get_plat(dev);
Marek Vasutfd83e762018-04-13 23:51:33 +0200722
723 return mmc_bind(dev, &plat->mmc, &plat->cfg);
724}
725
726int tmio_sd_probe(struct udevice *dev, u32 quirks)
727{
Simon Glassfa20e932020-12-03 16:55:20 -0700728 struct tmio_sd_plat *plat = dev_get_plat(dev);
Marek Vasutfd83e762018-04-13 23:51:33 +0200729 struct tmio_sd_priv *priv = dev_get_priv(dev);
730 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
731 fdt_addr_t base;
Marek Vasutda90a1b2018-06-13 08:02:55 +0200732 ulong mclk;
Marek Vasutfd83e762018-04-13 23:51:33 +0200733 int ret;
734
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900735 base = dev_read_addr(dev);
Marek Vasutfd83e762018-04-13 23:51:33 +0200736 if (base == FDT_ADDR_T_NONE)
737 return -EINVAL;
738
739 priv->regbase = devm_ioremap(dev, base, SZ_2K);
740 if (!priv->regbase)
741 return -ENOMEM;
742
Marek Vasutd4be38e2023-02-28 22:18:13 +0100743 if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
744 device_get_supply_regulator(dev, "vqmmc-supply",
745 &priv->vqmmc_dev);
746 if (priv->vqmmc_dev)
747 regulator_set_value(priv->vqmmc_dev, 3300000);
748 }
Marek Vasutfd83e762018-04-13 23:51:33 +0200749
Marek Vasutfd83e762018-04-13 23:51:33 +0200750 ret = mmc_of_parse(dev, &plat->cfg);
751 if (ret < 0) {
752 dev_err(dev, "failed to parse host caps\n");
753 return ret;
754 }
755
756 plat->cfg.name = dev->name;
757 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
758
759 if (quirks)
760 priv->caps = quirks;
761
762 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
763 TMIO_SD_VERSION_IP;
764 dev_dbg(dev, "version %x\n", priv->version);
765 if (priv->version >= 0x10) {
766 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
Marek Vasutd61f32e2023-10-22 23:40:43 +0200767 if (!(priv->caps & TMIO_SD_CAP_RCAR))
768 priv->caps |= TMIO_SD_CAP_DIV1024;
Marek Vasutfd83e762018-04-13 23:51:33 +0200769 }
770
771 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
772 NULL))
773 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
774
775 tmio_sd_host_init(priv);
776
Marek Vasutda90a1b2018-06-13 08:02:55 +0200777 mclk = tmio_sd_clk_get_rate(priv);
778
Marek Vasutfd83e762018-04-13 23:51:33 +0200779 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
Marek Vasutda90a1b2018-06-13 08:02:55 +0200780 plat->cfg.f_min = mclk /
Marek Vasutfd83e762018-04-13 23:51:33 +0200781 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
Marek Vasutda90a1b2018-06-13 08:02:55 +0200782 plat->cfg.f_max = mclk;
Marek Vasut6d6e6fe2019-03-18 23:43:10 +0100783 if (quirks & TMIO_SD_CAP_16BIT)
784 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
785 else
786 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
Marek Vasutfd83e762018-04-13 23:51:33 +0200787
788 upriv->mmc = &plat->mmc;
789
790 return 0;
791}