mmc: tmio: Make DMA transfer end bit configurable
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 2014920..0b6a284 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -347,12 +347,10 @@
/*
* The DMA READ completion flag position differs on Socionext
* and Renesas SoCs. It is bit 20 on Socionext SoCs and using
- * bit 17 is a hardware bug and forbidden. It is bit 17 on
- * Renesas SoCs and bit 20 does not work on them.
+ * bit 17 is a hardware bug and forbidden. It is either bit 17
+ * or bit 20 on Renesas SoCs, depending on SoC.
*/
- poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ?
- TMIO_SD_DMA_INFO1_END_RD :
- TMIO_SD_DMA_INFO1_END_RD2;
+ poll_flag = priv->read_poll_flag;
tmp |= TMIO_SD_DMA_MODE_DIR_RD;
} else {
buf = (void *)data->src;