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git01.mediatek.com / filogic / uboot / cc4ecdadec27073a3d6b0a84abbf9f883860ea70 / . / arch / sandbox / dts / sandbox.dts
blob: 12d3eff5fa73b2cbfa86498573ff3b7c69561ed3 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Main sandbox devicetree
4 */
5
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]6/dts-v1/;
7
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]8#include <config.h>
9
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]10/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]11 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]12 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]13 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]14 compatible = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]15
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]16 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]17 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]18 pci0 = &pcic;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]19 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]20 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]21 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]22 };
23
Simon Glass5e135d32022-10-20 18:23:15 -0600[diff] [blame]24 binman: binman {
25 };
26
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]27 memory {
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]28 reg = <0 CFG_SYS_SDRAM_SIZE>;
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]29 };
30
Heinrich Schuchardtad935702020-03-14 12:13:39 +0100[diff] [blame]31 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 ranges;
35
36 reservation_test0 {
37 size = <0x4000>;
38 alignment = <0x2000>;
39 };
40
41 reservation_test1: restest@a000 {
42 reg = <0x00d0a000 0x2000>;
43 };
44
45 reservation_test2: restest@7000 {
46 reg = <0x00d07000 0x1000>;
47 };
48 };
49
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]50 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]51 reg = <0 0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-some-ram;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]53 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]54 };
55
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]56 dsi_host: dsi_host {
57 compatible = "sandbox,dsi-host";
58 status = "okay";
59 };
60
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]61 ethrawbus {
62 compatible = "sandbox,eth-raw-bus";
63 skip-localhost = <0>;
64 };
65
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]66 eth@10002000 {
67 compatible = "sandbox,eth";
68 reg = <0x10002000 0x1000>;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]69 };
70
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]71 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]72 #address-cells = <1>;
73 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]74 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]75 compatible = "sandbox,i2c";
76 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glasscce3e3e2023-02-22 09:34:04 -0700[diff] [blame]79 bootph-pre-ram;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]80 };
81
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]82 pcic: pci@0 {
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]83 compatible = "sandbox,pci";
84 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]85 bus-range = <0x00 0xff>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
89 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]90 };
91
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]92 spi: spi@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-some-ram;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0 0>;
97 compatible = "sandbox,spi";
98 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]99 };
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]100};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]101
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]102#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]103#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]104#include "sandbox_pmic.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -0600[diff] [blame]105
Simon Glassf32c5b12023-02-22 09:34:05 -0700[diff] [blame]106#if IS_ENABLED(CONFIG_SUPPORT_VPL)
Simon Glass5e135d32022-10-20 18:23:15 -0600[diff] [blame]107#include "sandbox_vpl.dtsi"
108#endif