blob: ed46a9ad286c03a223adca505b8a672f676edeaa [file] [log] [blame]
Kever Yang34ead0f2019-07-09 22:05:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080012#include <ram.h>
13#include <spl.h>
14#include <version.h>
15#include <asm/io.h>
16#include <asm/arch-rockchip/bootrom.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Johan Jonkerfebb9692022-04-09 18:55:05 +020018#include <linux/kconfig.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080019
Pali Rohár6e1f0852021-08-02 15:18:38 +020020#if CONFIG_IS_ENABLED(BANNER_PRINT)
21#include <timestamp.h>
22#endif
23
Kever Yang34ead0f2019-07-09 22:05:55 +080024#define TIMER_LOAD_COUNT_L 0x00
25#define TIMER_LOAD_COUNT_H 0x04
26#define TIMER_CONTROL_REG 0x10
27#define TIMER_EN 0x1
28#define TIMER_FMODE BIT(0)
29#define TIMER_RMODE BIT(1)
30
31__weak void rockchip_stimer_init(void)
32{
Johan Jonker5180b1a2022-04-09 18:55:04 +020033#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
Kever Yang34ead0f2019-07-09 22:05:55 +080034 /* If Timer already enabled, don't re-init it */
35 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
36
37 if (reg & TIMER_EN)
38 return;
39
40#ifndef CONFIG_ARM64
41 asm volatile("mcr p15, 0, %0, c14, c0, 0"
Peng Fane7c59392022-04-13 17:47:22 +080042 : : "r"(CONFIG_COUNTER_FREQUENCY));
Kever Yang34ead0f2019-07-09 22:05:55 +080043#endif
44
45 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
46 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
47 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
48 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
49 TIMER_CONTROL_REG);
Johan Jonker5180b1a2022-04-09 18:55:04 +020050#endif
Kever Yang34ead0f2019-07-09 22:05:55 +080051}
52
53void board_init_f(ulong dummy)
54{
55 struct udevice *dev;
56 int ret;
57
Simon Glassf4d60392021-08-08 12:20:12 -060058#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
Kever Yang34ead0f2019-07-09 22:05:55 +080059 /*
60 * Debug UART can be used from here if required:
61 *
62 * debug_uart_init();
63 * printch('a');
64 * printhex8(0x1234);
65 * printascii("string");
66 */
67 debug_uart_init();
Chris Webb45dd8012019-07-19 14:23:55 +010068#ifdef CONFIG_TPL_BANNER_PRINT
Kever Yang34ead0f2019-07-09 22:05:55 +080069 printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
70 U_BOOT_TIME ")\n");
71#endif
Chris Webb45dd8012019-07-19 14:23:55 +010072#endif
Kever Yang34ead0f2019-07-09 22:05:55 +080073 ret = spl_early_init();
74 if (ret) {
75 debug("spl_early_init() failed: %d\n", ret);
76 hang();
77 }
78
79 /* Init secure timer */
80 rockchip_stimer_init();
Johan Jonkerfebb9692022-04-09 18:55:05 +020081
82 /* Init ARM arch timer */
83 if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
84 timer_init();
Kever Yang34ead0f2019-07-09 22:05:55 +080085
86 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
87 if (ret) {
88 printf("DRAM init failed: %d\n", ret);
89 return;
90 }
91}
92
Peng Fanaa050c52019-08-07 06:40:53 +000093int board_return_to_bootrom(struct spl_image_info *spl_image,
94 struct spl_boot_device *bootdev)
Kever Yang34ead0f2019-07-09 22:05:55 +080095{
96 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
Peng Fanaa050c52019-08-07 06:40:53 +000097
98 return 0;
Kever Yang34ead0f2019-07-09 22:05:55 +080099}
100
101u32 spl_boot_device(void)
102{
103 return BOOT_DEVICE_BOOTROM;
104}