blob: 3ff4d43c994df4990f7c10d769e41f38ad1fe827 [file] [log] [blame]
Peng Fancbe5d382021-08-07 16:01:13 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 NXP
4 */
5
6#include <common.h>
7#include <miiphy.h>
8#include <netdev.h>
9#include <asm/arch/imx8ulp-pins.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/pcc.h>
12#include <asm/arch/sys_proto.h>
13#include <miiphy.h>
14#include <netdev.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#if IS_ENABLED(CONFIG_FEC_MXC)
19#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
20static iomux_cfg_t const enet_clk_pads[] = {
21 IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
22 IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
23};
24
25static int setup_fec(void)
26{
27 /*
28 * Since ref clock and timestamp clock are from external,
29 * set the iomux prior the clock enablement
30 */
31 imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads));
32
33 /* Select enet time stamp clock: 001 - External Timestamp Clock */
34 cgc1_enet_stamp_sel(1);
35
36 /* enable FEC PCC */
37 pcc_clock_enable(4, ENET_PCC4_SLOT, true);
38 pcc_reset_peripheral(4, ENET_PCC4_SLOT, false);
39
40 return 0;
41}
42
43int board_phy_config(struct phy_device *phydev)
44{
45 if (phydev->drv->config)
46 phydev->drv->config(phydev);
47 return 0;
48}
49#endif
50
51int board_init(void)
52{
53 if (IS_ENABLED(CONFIG_FEC_MXC))
54 setup_fec();
55
56 return 0;
57}
58
59int board_early_init_f(void)
60{
61 return 0;
62}
63
64int board_late_init(void)
65{
66 return 0;
67}