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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhang8e697a02014-07-09 23:44:46 +03002/*
3 * K2HK EVM : Board initialization
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhang8e697a02014-07-09 23:44:46 +03007 */
8
9#include <common.h>
Vitaly Andrianov047e7802014-07-25 22:23:19 +030010#include <asm/arch/clock.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030011#include <asm/arch/hardware.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030012#include <asm/ti-common/keystone_net.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030013
Hao Zhang8e697a02014-07-09 23:44:46 +030014unsigned int external_clk[ext_clk_count] = {
15 [sys_clk] = 122880000,
16 [alt_core_clk] = 125000000,
17 [pa_clk] = 122880000,
18 [tetris_clk] = 125000000,
19 [ddr3a_clk] = 100000000,
20 [ddr3b_clk] = 100000000,
Hao Zhang8e697a02014-07-09 23:44:46 +030021};
22
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053023unsigned int get_external_clk(u32 clk)
24{
25 unsigned int clk_freq;
26
27 switch (clk) {
28 case sys_clk:
29 clk_freq = 122880000;
30 break;
31 case alt_core_clk:
32 clk_freq = 125000000;
33 break;
34 case pa_clk:
35 clk_freq = 122880000;
36 break;
37 case tetris_clk:
38 clk_freq = 125000000;
39 break;
40 case ddr3a_clk:
41 clk_freq = 100000000;
42 break;
43 case ddr3b_clk:
44 clk_freq = 100000000;
45 break;
46 default:
47 clk_freq = 0;
48 break;
49 }
50
51 return clk_freq;
52}
53
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053054static struct pll_init_data core_pll_config[NUM_SPDS] = {
55 [SPD800] = CORE_PLL_799,
56 [SPD1000] = CORE_PLL_999,
57 [SPD1200] = CORE_PLL_1200,
Vitaly Andrianov047e7802014-07-25 22:23:19 +030058};
59
Lokesh Vutla70438fc2015-07-28 14:16:43 +053060s16 divn_val[16] = {
61 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
62};
63
Vitaly Andrianov047e7802014-07-25 22:23:19 +030064static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053065 [SPD800] = TETRIS_PLL_800,
66 [SPD1000] = TETRIS_PLL_1000,
67 [SPD1200] = TETRIS_PLL_1200,
68 [SPD1350] = TETRIS_PLL_1350,
69 [SPD1400] = TETRIS_PLL_1400,
Hao Zhang8e697a02014-07-09 23:44:46 +030070};
71
Vitaly Andrianov047e7802014-07-25 22:23:19 +030072static struct pll_init_data pa_pll_config =
73 PASS_PLL_983;
74
Lokesh Vutla79a94a22015-07-28 14:16:46 +053075struct pll_init_data *get_pll_init_data(int pll)
76{
77 int speed;
78 struct pll_init_data *data;
79
80 switch (pll) {
81 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060082 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053083 data = &core_pll_config[speed];
84 break;
85 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060086 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053087 data = &tetris_pll_config[speed];
88 break;
89 case PASS_PLL:
90 data = &pa_pll_config;
91 break;
92 default:
93 data = NULL;
94 }
95
96 return data;
97}
98
Hao Zhang8e697a02014-07-09 23:44:46 +030099#ifdef CONFIG_BOARD_EARLY_INIT_F
100int board_early_init_f(void)
101{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530102 init_plls();
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300103
Hao Zhang8e697a02014-07-09 23:44:46 +0300104 return 0;
105}
106#endif
Hao Zhang95948202014-10-22 16:32:31 +0300107
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +0200108#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -0500109int board_fit_config_name_match(const char *name)
110{
111 if (!strcmp(name, "keystone-k2hk-evm"))
112 return 0;
113
114 return -1;
115}
116#endif
117
Hao Zhang95948202014-10-22 16:32:31 +0300118#ifdef CONFIG_SPL_BUILD
Hao Zhang95948202014-10-22 16:32:31 +0300119void spl_init_keystone_plls(void)
120{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530121 init_plls();
Hao Zhang95948202014-10-22 16:32:31 +0300122}
123#endif