blob: c7330996d1abecd0e437679b14ab3dd9c0c24e3f [file] [log] [blame]
Hao Zhang8e697a02014-07-09 23:44:46 +03001/*
2 * K2HK EVM : Board initialization
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
Vitaly Andrianov047e7802014-07-25 22:23:19 +030011#include <asm/arch/clock.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030012#include <asm/arch/hardware.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030013#include <asm/ti-common/keystone_net.h>
Hao Zhang8e697a02014-07-09 23:44:46 +030014
15DECLARE_GLOBAL_DATA_PTR;
16
17unsigned int external_clk[ext_clk_count] = {
18 [sys_clk] = 122880000,
19 [alt_core_clk] = 125000000,
20 [pa_clk] = 122880000,
21 [tetris_clk] = 125000000,
22 [ddr3a_clk] = 100000000,
23 [ddr3b_clk] = 100000000,
Hao Zhang8e697a02014-07-09 23:44:46 +030024};
25
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053026unsigned int get_external_clk(u32 clk)
27{
28 unsigned int clk_freq;
29
30 switch (clk) {
31 case sys_clk:
32 clk_freq = 122880000;
33 break;
34 case alt_core_clk:
35 clk_freq = 125000000;
36 break;
37 case pa_clk:
38 clk_freq = 122880000;
39 break;
40 case tetris_clk:
41 clk_freq = 125000000;
42 break;
43 case ddr3a_clk:
44 clk_freq = 100000000;
45 break;
46 case ddr3b_clk:
47 clk_freq = 100000000;
48 break;
49 default:
50 clk_freq = 0;
51 break;
52 }
53
54 return clk_freq;
55}
56
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053057static struct pll_init_data core_pll_config[NUM_SPDS] = {
58 [SPD800] = CORE_PLL_799,
59 [SPD1000] = CORE_PLL_999,
60 [SPD1200] = CORE_PLL_1200,
Vitaly Andrianov047e7802014-07-25 22:23:19 +030061};
62
Lokesh Vutla70438fc2015-07-28 14:16:43 +053063s16 divn_val[16] = {
64 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
65};
66
Vitaly Andrianov047e7802014-07-25 22:23:19 +030067static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053068 [SPD800] = TETRIS_PLL_800,
69 [SPD1000] = TETRIS_PLL_1000,
70 [SPD1200] = TETRIS_PLL_1200,
71 [SPD1350] = TETRIS_PLL_1350,
72 [SPD1400] = TETRIS_PLL_1400,
Hao Zhang8e697a02014-07-09 23:44:46 +030073};
74
Vitaly Andrianov047e7802014-07-25 22:23:19 +030075static struct pll_init_data pa_pll_config =
76 PASS_PLL_983;
77
Lokesh Vutla79a94a22015-07-28 14:16:46 +053078struct pll_init_data *get_pll_init_data(int pll)
79{
80 int speed;
81 struct pll_init_data *data;
82
83 switch (pll) {
84 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060085 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053086 data = &core_pll_config[speed];
87 break;
88 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060089 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053090 data = &tetris_pll_config[speed];
91 break;
92 case PASS_PLL:
93 data = &pa_pll_config;
94 break;
95 default:
96 data = NULL;
97 }
98
99 return data;
100}
101
Hao Zhang8e697a02014-07-09 23:44:46 +0300102#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
103struct eth_priv_t eth_priv_cfg[] = {
104 {
105 .int_name = "K2HK_EMAC",
106 .rx_flow = 22,
107 .phy_addr = 0,
108 .slave_port = 1,
109 .sgmii_link_type = SGMII_LINK_MAC_PHY,
Mugunthan V Nd44bb342015-09-19 16:26:48 +0530110 .phy_if = PHY_INTERFACE_MODE_SGMII,
Hao Zhang8e697a02014-07-09 23:44:46 +0300111 },
112 {
113 .int_name = "K2HK_EMAC1",
114 .rx_flow = 23,
115 .phy_addr = 1,
116 .slave_port = 2,
117 .sgmii_link_type = SGMII_LINK_MAC_PHY,
Mugunthan V Nd44bb342015-09-19 16:26:48 +0530118 .phy_if = PHY_INTERFACE_MODE_SGMII,
Hao Zhang8e697a02014-07-09 23:44:46 +0300119 },
120 {
121 .int_name = "K2HK_EMAC2",
122 .rx_flow = 24,
123 .phy_addr = 2,
124 .slave_port = 3,
125 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
Mugunthan V Nd44bb342015-09-19 16:26:48 +0530126 .phy_if = PHY_INTERFACE_MODE_SGMII,
Hao Zhang8e697a02014-07-09 23:44:46 +0300127 },
128 {
129 .int_name = "K2HK_EMAC3",
130 .rx_flow = 25,
131 .phy_addr = 3,
132 .slave_port = 4,
133 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
Mugunthan V Nd44bb342015-09-19 16:26:48 +0530134 .phy_if = PHY_INTERFACE_MODE_SGMII,
Hao Zhang8e697a02014-07-09 23:44:46 +0300135 },
136};
137
138int get_num_eth_ports(void)
139{
140 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
141}
142#endif
143
144#ifdef CONFIG_BOARD_EARLY_INIT_F
145int board_early_init_f(void)
146{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530147 init_plls();
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300148
Hao Zhang8e697a02014-07-09 23:44:46 +0300149 return 0;
150}
151#endif
Hao Zhang95948202014-10-22 16:32:31 +0300152
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -0500153#if defined(CONFIG_FIT_EMBED)
154int board_fit_config_name_match(const char *name)
155{
156 if (!strcmp(name, "keystone-k2hk-evm"))
157 return 0;
158
159 return -1;
160}
161#endif
162
Hao Zhang95948202014-10-22 16:32:31 +0300163#ifdef CONFIG_SPL_BUILD
Hao Zhang95948202014-10-22 16:32:31 +0300164void spl_init_keystone_plls(void)
165{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530166 init_plls();
Hao Zhang95948202014-10-22 16:32:31 +0300167}
168#endif