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git01.mediatek.com / filogic / uboot / cb2a32a90534e6a15ca2d8da0072498e9688a11c / . / arch / sandbox / dts / sandbox.dts
blob: 21f00fcab5ee6ca7747e672174c616246a98a589 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Main sandbox devicetree
4 */
5
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]6/dts-v1/;
7
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]8#include <config.h>
9
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]10/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]11 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]12 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]13 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]14 compatible = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]15
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]16 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]17 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]18 pci0 = &pcic;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]19 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]20 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]21 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]22 };
23
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]24 memory {
25 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
26 };
27
Heinrich Schuchardtad935702020-03-14 12:13:39 +0100[diff] [blame]28 reserved-memory {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 reservation_test0 {
34 size = <0x4000>;
35 alignment = <0x2000>;
36 };
37
38 reservation_test1: restest@a000 {
39 reg = <0x00d0a000 0x2000>;
40 };
41
42 reservation_test2: restest@7000 {
43 reg = <0x00d07000 0x1000>;
44 };
45 };
46
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]47 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]48 reg = <0 0>;
Simon Glasse98524a2020-12-19 10:39:56 -0700[diff] [blame]49 u-boot,dm-pre-proper;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]50 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]51 };
52
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]53 dsi_host: dsi_host {
54 compatible = "sandbox,dsi-host";
55 status = "okay";
56 };
57
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]58 ethrawbus {
59 compatible = "sandbox,eth-raw-bus";
60 skip-localhost = <0>;
61 };
62
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]63 eth@10002000 {
64 compatible = "sandbox,eth";
65 reg = <0x10002000 0x1000>;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]66 };
67
Simon Glass1b4bc152022-04-24 23:31:21 -0600[diff] [blame]68 host-fs {
69 compatible = "sandbox,bootdev-host";
70 };
71
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]72 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]73 #address-cells = <1>;
74 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]75 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]76 compatible = "sandbox,i2c";
77 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glass4d4558e2020-10-03 11:31:36 -0600[diff] [blame]80 u-boot,dm-pre-reloc;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]81 };
82
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]83 pcic: pci@0 {
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]84 compatible = "sandbox,pci";
85 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]86 bus-range = <0x00 0xff>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]87 #address-cells = <3>;
88 #size-cells = <2>;
89 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
90 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]91 };
92
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]93 spi: spi@0 {
Simon Glasse98524a2020-12-19 10:39:56 -0700[diff] [blame]94 u-boot,dm-pre-proper;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <0 0>;
98 compatible = "sandbox,spi";
99 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]100 };
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]101};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]102
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]103#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]104#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]105#include "sandbox_pmic.dtsi"