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git01.mediatek.com / filogic / uboot / cafb9b42586031ec474add8e3acb30a1d7cb299e / . / board / amcc / katmai / init.S
blob: 4a42f1fc49076d2aa4f3d0061c5aeea915100a4a [file] [log] [blame]
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <ppc_asm.tmpl>
27#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]28#include <asm/mmu.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]29#include <asm/ppc4xx.h>
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]30
31/**************************************************************************
32 * TLB TABLE
33 *
34 * This table is used by the cpu boot code to setup the initial tlb
35 * entries. Rather than make broad assumptions in the cpu source tree,
36 * this table lets each board set things up however they like.
37 *
38 * Pointer to the table is returned in r1
39 *
40 *************************************************************************/
41
42 .section .bootpg,"ax"
43
44/**************************************************************************
45 * TLB table for revA
46 *************************************************************************/
47 .globl tlbtabA
48tlbtabA:
49 tlbtab_start
Stefan Roese3f7b8612007-03-08 10:07:18 +0100[diff] [blame]50
51 /*
52 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
53 * speed up boot process. It is patched after relocation to enable SA_I
54 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]55 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]56
57 /*
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
60 * routine.
61 */
62
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]63 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
64 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]65
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]66 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
67 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
68 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
69 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]70
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]71 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
72 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
73 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
74 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
75 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
76 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]77 tlbtab_end
78
79/**************************************************************************
80 * TLB table for revB
81 *
82 * Notice: revB of the 440SPe chip is very strict about PLB real addresses
83 * and ranges to be mapped for config space: it seems to only work with
84 * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
85 * set otherwise) while revA uses c_nnnn_nnnn.
86 *************************************************************************/
87 .globl tlbtabB
88tlbtabB:
89 tlbtab_start
Stefan Roese3f7b8612007-03-08 10:07:18 +0100[diff] [blame]90
91 /*
92 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
93 * speed up boot process. It is patched after relocation to enable SA_I
94 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]95 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]96
97 /*
98 * TLB entries for SDRAM are not needed on this platform.
99 * They are dynamically generated in the SPD DDR(2) detection
100 * routine.
101 */
102
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]103 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]104
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]105 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]106
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]107 tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]108
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]109 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
110 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
111 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]112
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]113 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
114 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
115 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
116 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
117 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
118 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]119 tlbtab_end