| Stefan Roese | a8856e3 | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #include <ppc_asm.tmpl> |
| 27 | #include <config.h> |
| 28 | #include <asm-ppc/mmu.h> |
| 29 | |
| 30 | /************************************************************************** |
| 31 | * TLB TABLE |
| 32 | * |
| 33 | * This table is used by the cpu boot code to setup the initial tlb |
| 34 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 35 | * this table lets each board set things up however they like. |
| 36 | * |
| 37 | * Pointer to the table is returned in r1 |
| 38 | * |
| 39 | *************************************************************************/ |
| 40 | |
| 41 | .section .bootpg,"ax" |
| 42 | |
| 43 | /************************************************************************** |
| 44 | * TLB table for revA |
| 45 | *************************************************************************/ |
| 46 | .globl tlbtabA |
| 47 | tlbtabA: |
| 48 | tlbtab_start |
| Stefan Roese | 3f7b861 | 2007-03-08 10:07:18 +0100 | [diff] [blame^] | 49 | |
| 50 | /* |
| 51 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 52 | * speed up boot process. It is patched after relocation to enable SA_I |
| 53 | */ |
| Stefan Roese | a8856e3 | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 54 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) |
| 55 | |
| 56 | /* |
| 57 | * TLB entries for SDRAM are not needed on this platform. |
| 58 | * They are dynamically generated in the SPD DDR(2) detection |
| 59 | * routine. |
| 60 | */ |
| 61 | |
| 62 | tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) |
| 63 | tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) |
| 64 | |
| 65 | tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 66 | tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 67 | tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 68 | tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 69 | |
| 70 | tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 71 | tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 72 | tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 73 | tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 74 | tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 75 | tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 76 | tlbtab_end |
| 77 | |
| 78 | /************************************************************************** |
| 79 | * TLB table for revB |
| 80 | * |
| 81 | * Notice: revB of the 440SPe chip is very strict about PLB real addresses |
| 82 | * and ranges to be mapped for config space: it seems to only work with |
| 83 | * d_nnnn_nnnn range (hangs the core upon config transaction attempts when |
| 84 | * set otherwise) while revA uses c_nnnn_nnnn. |
| 85 | *************************************************************************/ |
| 86 | .globl tlbtabB |
| 87 | tlbtabB: |
| 88 | tlbtab_start |
| Stefan Roese | 3f7b861 | 2007-03-08 10:07:18 +0100 | [diff] [blame^] | 89 | |
| 90 | /* |
| 91 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 92 | * speed up boot process. It is patched after relocation to enable SA_I |
| 93 | */ |
| Stefan Roese | a8856e3 | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 94 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) |
| 95 | |
| 96 | /* |
| 97 | * TLB entries for SDRAM are not needed on this platform. |
| 98 | * They are dynamically generated in the SPD DDR(2) detection |
| 99 | * routine. |
| 100 | */ |
| 101 | |
| 102 | tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) |
| 103 | |
| 104 | tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) |
| 105 | |
| 106 | tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) |
| 107 | |
| 108 | tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 109 | tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 110 | tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 111 | |
| 112 | tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 113 | tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 114 | tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 115 | tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 116 | tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 117 | tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 118 | tlbtab_end |