| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 2 | /* |
| 3 | * Keystone2: DDR3 initialization |
| 4 | * |
| 5 | * (C) Copyright 2014 |
| 6 | * Texas Instruments Incorporated, <www.ti.com> |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 7 | */ |
| 8 | |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 9 | #include "ddr3_cfg.h" |
| 10 | #include <asm/arch/ddr3.h> |
| 11 | |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 12 | static struct pll_init_data ddr3_400 = DDR3_PLL_400; |
| 13 | |
| Vitaly Andrianov | a9554d6 | 2015-02-11 14:07:58 -0500 | [diff] [blame] | 14 | u32 ddr3_init(void) |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 15 | { |
| 16 | init_pll(&ddr3_400); |
| 17 | |
| 18 | /* No SO-DIMM, 2GB discreet DDR */ |
| 19 | printf("DRAM: 2 GiB\n"); |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 20 | |
| 21 | /* Reset DDR3 PHY after PLL enabled */ |
| 22 | ddr3_reset_ddrphy(); |
| 23 | |
| 24 | ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); |
| 25 | ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 26 | |
| Vitaly Andrianov | a9554d6 | 2015-02-11 14:07:58 -0500 | [diff] [blame] | 27 | return 2; |
| Hao Zhang | c13cbcf | 2014-10-22 16:32:33 +0300 | [diff] [blame] | 28 | } |