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Bo Shen42aafb32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shen42aafb32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen337a2d82013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shen42aafb32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shen42aafb32012-07-05 17:21:46 +000021
Bo Shen42aafb32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
26#define CONFIG_BOARD_EARLY_INIT_F
27#define CONFIG_DISPLAY_CPUINFO
28
29/* general purpose I/O */
30#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
31#define CONFIG_AT91_GPIO
32
33/* serial console */
34#define CONFIG_ATMEL_USART
35#define CONFIG_USART_BASE ATMEL_BASE_DBGU
36#define CONFIG_USART_ID ATMEL_ID_SYS
37
38/* LCD */
39#define CONFIG_LCD
40#define LCD_BPP LCD_COLOR16
41#define LCD_OUTPUT_BPP 24
42#define CONFIG_LCD_LOGO
Bo Shen42aafb32012-07-05 17:21:46 +000043#define CONFIG_LCD_INFO
44#define CONFIG_LCD_INFO_BELOW_LOGO
45#define CONFIG_SYS_WHITE_ON_BLACK
46#define CONFIG_ATMEL_HLCD
47#define CONFIG_ATMEL_LCD_RGB565
48#define CONFIG_SYS_CONSOLE_IS_IN_ENV
49
50#define CONFIG_BOOTDELAY 3
51
52/*
53 * BOOTP options
54 */
55#define CONFIG_BOOTP_BOOTFILESIZE
56#define CONFIG_BOOTP_BOOTPATH
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_HOSTNAME
59
Bo Shen963a2b12013-12-10 16:14:02 +080060/* no NOR flash */
61#define CONFIG_SYS_NO_FLASH
62
Bo Shen42aafb32012-07-05 17:21:46 +000063/*
64 * Command line configuration.
65 */
Bo Shen42aafb32012-07-05 17:21:46 +000066#define CONFIG_CMD_NAND
Richard Genoud1e34e832012-11-29 23:18:34 +000067
68/*
69 * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
70 * NB: in this case, USB 1.1 devices won't be recognized.
71 */
72
Bo Shen42aafb32012-07-05 17:21:46 +000073/* SDRAM */
74#define CONFIG_NR_DRAM_BANKS 1
75#define CONFIG_SYS_SDRAM_BASE 0x20000000
76#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
77
78#define CONFIG_SYS_INIT_SP_ADDR \
79 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
80
81/* DataFlash */
Bo Shen4a73e582012-08-19 20:32:24 +000082#ifdef CONFIG_CMD_SF
83#define CONFIG_ATMEL_SPI
Bo Shen4a73e582012-08-19 20:32:24 +000084#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shen42aafb32012-07-05 17:21:46 +000085#endif
86
Bo Shen42aafb32012-07-05 17:21:46 +000087/* NAND flash */
88#ifdef CONFIG_CMD_NAND
89#define CONFIG_NAND_ATMEL
90#define CONFIG_SYS_MAX_NAND_DEVICE 1
91#define CONFIG_SYS_NAND_BASE 0x40000000
92#define CONFIG_SYS_NAND_DBW_8 1
93/* our ALE is AD21 */
94#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
95/* our CLE is AD22 */
96#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
97#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
98#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
99
Wu, Joshdd359a12012-08-23 00:05:38 +0000100/* PMECC & PMERRLOC */
101#define CONFIG_ATMEL_NAND_HWECC 1
102#define CONFIG_ATMEL_NAND_HW_PMECC 1
103#define CONFIG_PMECC_CAP 2
104#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdd359a12012-08-23 00:05:38 +0000105
Bo Shen591ef582013-06-26 10:48:53 +0800106#define CONFIG_CMD_NAND_TRIMFFS
107
Bo Shen42aafb32012-07-05 17:21:46 +0000108#define CONFIG_MTD_DEVICE
109#define CONFIG_CMD_MTDPARTS
110#define CONFIG_MTD_PARTITIONS
111#define CONFIG_RBTREE
112#define CONFIG_LZO
113#define CONFIG_CMD_UBI
114#define CONFIG_CMD_UBIFS
115#endif
116
Wu, Joshe32c6612012-09-13 22:22:05 +0000117/* MMC */
118#ifdef CONFIG_CMD_MMC
119#define CONFIG_MMC
Wu, Joshe32c6612012-09-13 22:22:05 +0000120#define CONFIG_GENERIC_MMC
121#define CONFIG_GENERIC_ATMEL_MCI
Richard Genoudfa2dbe72012-11-29 23:18:33 +0000122#endif
123
124/* FAT */
125#ifdef CONFIG_CMD_FAT
Wu, Joshe32c6612012-09-13 22:22:05 +0000126#define CONFIG_DOS_PARTITION
127#endif
128
Bo Shen42aafb32012-07-05 17:21:46 +0000129/* Ethernet */
130#define CONFIG_MACB
131#define CONFIG_RMII
132#define CONFIG_NET_RETRY_COUNT 20
133#define CONFIG_MACB_SEARCH_PHY
134
Richard Genoud1e34e832012-11-29 23:18:34 +0000135/* USB */
136#ifdef CONFIG_CMD_USB
137#ifdef CONFIG_USB_EHCI
138#define CONFIG_USB_EHCI_ATMEL
139#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
140#else
Bo Shen4a985df2013-10-21 16:14:00 +0800141#define CONFIG_USB_ATMEL
142#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoud1e34e832012-11-29 23:18:34 +0000143#define CONFIG_USB_OHCI_NEW
144#define CONFIG_SYS_USB_OHCI_CPU_INIT
145#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
146#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
147#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
148#endif
Richard Genoud1e34e832012-11-29 23:18:34 +0000149#define CONFIG_USB_STORAGE
150#endif
151
Bo Shen42aafb32012-07-05 17:21:46 +0000152#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
153
154#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
155#define CONFIG_SYS_MEMTEST_END 0x26e00000
156
157#ifdef CONFIG_SYS_USE_NANDFLASH
158/* bootstrap + u-boot + env + linux in nandflash */
159#define CONFIG_ENV_IS_IN_NAND
160#define CONFIG_ENV_OFFSET 0xc0000
161#define CONFIG_ENV_OFFSET_REDUND 0x100000
162#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
163#define CONFIG_BOOTCOMMAND "nand read " \
164 "0x22000000 0x200000 0x300000; " \
165 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000166#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen4a73e582012-08-19 20:32:24 +0000167/* bootstrap + u-boot + env + linux in spi flash */
168#define CONFIG_ENV_IS_IN_SPI_FLASH
169#define CONFIG_ENV_OFFSET 0x5000
170#define CONFIG_ENV_SIZE 0x3000
171#define CONFIG_ENV_SECT_SIZE 0x1000
172#define CONFIG_ENV_SPI_MAX_HZ 30000000
173#define CONFIG_BOOTCOMMAND "sf probe 0; " \
174 "sf read 0x22000000 0x100000 0x300000; " \
175 "bootm 0x22000000"
Bo Shen0a9f8ac2012-12-06 21:37:04 +0000176#elif defined(CONFIG_SYS_USE_DATAFLASH)
177/* bootstrap + u-boot + env + linux in data flash */
178#define CONFIG_ENV_IS_IN_SPI_FLASH
179#define CONFIG_ENV_OFFSET 0x4200
180#define CONFIG_ENV_SIZE 0x4200
181#define CONFIG_ENV_SECT_SIZE 0x210
182#define CONFIG_ENV_SPI_MAX_HZ 30000000
183#define CONFIG_BOOTCOMMAND "sf probe 0; " \
184 "sf read 0x22000000 0x84000 0x294000; " \
185 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000186#else /* CONFIG_SYS_USE_MMC */
187/* bootstrap + u-boot + env + linux in mmc */
Wu, Joshdf0ef742015-01-20 10:33:33 +0800188#define CONFIG_ENV_IS_IN_FAT
189#define CONFIG_FAT_WRITE
190#define FAT_ENV_INTERFACE "mmc"
191#define FAT_ENV_FILE "uboot.env"
192#define FAT_ENV_DEVICE_AND_PART "0"
193#define CONFIG_ENV_SIZE 0x4000
Bo Shen42aafb32012-07-05 17:21:46 +0000194#endif
195
Wu, Josh9d681892012-11-02 00:17:27 +0000196#ifdef CONFIG_SYS_USE_MMC
Bo Shen42aafb32012-07-05 17:21:46 +0000197#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
198 "mtdparts=atmel_nand:" \
199 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
Wu, Josh9d681892012-11-02 00:17:27 +0000200 "root=/dev/mmcblk0p2 " \
201 "rw rootfstype=ext4 rootwait"
202#else
Bo Shena8fd0632013-02-20 00:16:25 +0000203#define CONFIG_BOOTARGS \
204 "console=ttyS0,115200 earlyprintk " \
205 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
206 "256k(env),256k(env_redundant),256k(spare)," \
207 "512k(dtb),6M(kernel)ro,-(rootfs) " \
208 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Josh9d681892012-11-02 00:17:27 +0000209#endif
Bo Shen42aafb32012-07-05 17:21:46 +0000210
211#define CONFIG_BAUDRATE 115200
212
Bo Shen42aafb32012-07-05 17:21:46 +0000213#define CONFIG_SYS_CBSIZE 256
214#define CONFIG_SYS_MAXARGS 16
Bo Shen42aafb32012-07-05 17:21:46 +0000215#define CONFIG_SYS_LONGHELP
216#define CONFIG_CMDLINE_EDITING
217#define CONFIG_AUTO_COMPLETE
Bo Shen42aafb32012-07-05 17:21:46 +0000218
219/*
220 * Size of malloc() pool
221 */
222#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
223
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800224/* SPL */
225#define CONFIG_SPL_FRAMEWORK
226#define CONFIG_SPL_TEXT_BASE 0x300000
227#define CONFIG_SPL_MAX_SIZE 0x6000
228#define CONFIG_SPL_STACK 0x308000
229
230#define CONFIG_SPL_BSS_START_ADDR 0x20000000
231#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
232#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
233#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
234
235#define CONFIG_SPL_LIBCOMMON_SUPPORT
236#define CONFIG_SPL_LIBGENERIC_SUPPORT
237#define CONFIG_SPL_GPIO_SUPPORT
238#define CONFIG_SPL_SERIAL_SUPPORT
239
240#define CONFIG_SPL_BOARD_INIT
241#define CONFIG_SYS_MONITOR_LEN (512 << 10)
242
243#define CONFIG_SYS_MASTER_CLOCK 132096000
244#define CONFIG_SYS_AT91_PLLA 0x20c73f03
245#define CONFIG_SYS_MCKR 0x1301
246#define CONFIG_SYS_MCKR_CSS 0x1302
247
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800248#ifdef CONFIG_SYS_USE_MMC
249#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
250#define CONFIG_SPL_MMC_SUPPORT
251#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
252#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
253#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
254#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
255#define CONFIG_SPL_FAT_SUPPORT
256#define CONFIG_SPL_LIBDISK_SUPPORT
257
258#elif CONFIG_SYS_USE_NANDFLASH
259#define CONFIG_SPL_NAND_SUPPORT
260#define CONFIG_SPL_NAND_DRIVERS
261#define CONFIG_SPL_NAND_BASE
262#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
263#define CONFIG_SYS_NAND_5_ADDR_CYCLE
264#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
265#define CONFIG_SYS_NAND_PAGE_COUNT 64
266#define CONFIG_SYS_NAND_OOBSIZE 64
267#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
268#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
269#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
270
271#elif CONFIG_SYS_USE_SPIFLASH
272#define CONFIG_SPL_SPI_SUPPORT
273#define CONFIG_SPL_SPI_FLASH_SUPPORT
274#define CONFIG_SPL_SPI_LOAD
275#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
276
277#endif
278
Bo Shen42aafb32012-07-05 17:21:46 +0000279#endif