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git01.mediatek.com / filogic / uboot / ca012b9b0c8611bbc1df999a95a4fd2ab3e4f03a / . / arch / arm / dts / k3-am642-r5-sk.dts
blob: daa483a781150f9cc42033bb81a31c6f43f38a84 [file] [log] [blame]
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]6#include "k3-am642-sk.dts"
Dave Gerlachd7760d02022-09-29 12:35:48 -0500[diff] [blame]7#include "k3-am64-sk-lp4-1600MTs.dtsi"
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]8#include "k3-am64-ddr.dtsi"
9
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10#include "k3-am642-sk-u-boot.dtsi"
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]11
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]12/ {
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]13 aliases {
14 remoteproc0 = &sysctrler;
15 remoteproc1 = &a53_0;
16 };
17
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]18 a53_0: a53@0 {
19 compatible = "ti,am654-rproc";
20 reg = <0x00 0x00a90000 0x00 0x10>;
21 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhrya6c9a6b2023-04-14 09:47:56 +0530[diff] [blame]22 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
23 <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]24 resets = <&k3_reset 135 0>;
25 clocks = <&k3_clks 61 0>;
26 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
27 assigned-clock-parents = <&k3_clks 61 2>;
28 assigned-clock-rates = <200000000>, <1000000000>;
29 ti,sci = <&dmsc>;
30 ti,sci-proc-id = <32>;
31 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]33 };
34
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]35 clk_200mhz: dummy-clock-200mhz {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]40 };
41};
42
43&cbass_main {
44 sysctrler: sysctrler {
45 compatible = "ti,am654-system-controller";
46 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
47 mbox-names = "tx", "rx";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]49 };
50};
51
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]52&main_esm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Hari Nagalla789225e2022-03-09 14:42:29 -0600[diff] [blame]54};
55
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]56&cbass_mcu {
57 bootph-pre-ram;
58};
59
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]60&mcu_esm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]62};
63
64&dmsc {
65 mboxes= <&secure_proxy_main 0>,
66 <&secure_proxy_main 1>,
67 <&secure_proxy_main 0>;
68 mbox-names = "rx", "tx", "notify";
69 ti,host-id = <35>;
70 ti,secure-host;
71};
72
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]73&sdhci1 {
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]74 clocks = <&clk_200mhz>;
75 clock-names = "clk_xin";
Lokesh Vutla86106ed2021-05-06 16:45:00 +0530[diff] [blame]76};
77
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]78&serdes_wiz0 {
79 status = "okay";
80};
81
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]82/* UART is initialized before SYSFW is started
83 * so we can't do any power-domain/clock operations.
84 * Delete clock/power-domain properties to avoid
85 * UART init failure
86 */
87&main_uart0 {
88 /delete-property/ power-domains;
89 /delete-property/ clocks;
90 /delete-property/ clock-names;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]91};
92
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]93/* timer init is called as part of rproc_start() while
94 * starting System Firmware, so any clock/power-domain
95 * operations will fail as SYSFW is not yet up and running.
96 * Delete all clock/power-domain properties to avoid
97 * timer init failure.
98 * This is an always on timer at 20MHz.
99 */
100&main_timer0 {
101 /delete-property/ clocks;
102 /delete-property/ assigned-clocks;
103 /delete-property/ assigned-clock-parents;
104 /delete-property/ power-domains;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]105};