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git01.mediatek.com / filogic / uboot / c9eb6bd05d8889131bde446bb489b34566ec7d40 / . / arch / arm / dts / mt7629-rfb.dts
blob: 82f6a34162657b6df68538aa77edc20f8a8417ee [file] [log] [blame]
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]1/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include "mt7629.dtsi"
developerc69976c2020-01-10 16:30:34 +0800[diff] [blame]10#include "mt7629-rfb-u-boot.dtsi"
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]11
12/ {
13 model = "MediaTek MT7629 RFB";
14 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
15
16 aliases {
developer9b8267a2021-01-20 15:31:34 +0800[diff] [blame]17 spi0 = &snor;
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]18 };
19
20 chosen {
21 stdout-path = &uart0;
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]22 };
23};
24
developere43f3c72018-12-20 16:12:55 +0800[diff] [blame]25&eth {
26 status = "okay";
developer8ef69482020-06-19 19:17:17 +0800[diff] [blame]27 mediatek,gmac-id = <0>;
28 phy-mode = "sgmii";
29 mediatek,switch = "mt7531";
30 reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
developere43f3c72018-12-20 16:12:55 +0800[diff] [blame]31
developer8ef69482020-06-19 19:17:17 +0800[diff] [blame]32 fixed-link {
33 speed = <1000>;
34 full-duplex;
developere43f3c72018-12-20 16:12:55 +0800[diff] [blame]35 };
36};
37
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]38&pinctrl {
developer12687552021-03-05 10:27:46 +0800[diff] [blame]39 state_default: pinmux_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-all;
developer12687552021-03-05 10:27:46 +0800[diff] [blame]41
42 mux {
43 function = "jtag";
44 groups = "ephy_leds_jtag";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
developer12687552021-03-05 10:27:46 +0800[diff] [blame]46 };
47 };
48
developer68743392019-07-22 10:35:10 +0800[diff] [blame]49 snfi_pins: snfi-pins {
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]50 mux {
51 function = "flash";
developer68743392019-07-22 10:35:10 +0800[diff] [blame]52 groups = "snfi";
53 };
54 };
55
56 snor_pins: snor-pins {
57 mux {
58 function = "flash";
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]59 groups = "spi_nor";
60 };
61 };
62
63 uart0_pins: uart0-default {
64 mux {
65 function = "uart";
66 groups = "uart0_txd_rxd";
67 };
68 };
69
70 watchdog_pins: watchdog-default {
71 mux {
72 function = "watchdog";
73 groups = "watchdog";
74 };
75 };
76};
77
developer68743392019-07-22 10:35:10 +0800[diff] [blame]78&snfi {
79 pinctrl-names = "default", "snfi";
80 pinctrl-0 = <&snor_pins>;
81 pinctrl-1 = <&snfi_pins>;
developer9b8267a2021-01-20 15:31:34 +0800[diff] [blame]82 status = "disabled";
83
84 spi-flash@0{
85 compatible = "jedec,spi-nor";
86 reg = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-all;
developer9b8267a2021-01-20 15:31:34 +0800[diff] [blame]88 };
89};
90
91&snor {
92 pinctrl-names = "default";
93 pinctrl-0 = <&snor_pins>;
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]94 status = "okay";
95
96 spi-flash@0{
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]97 compatible = "jedec,spi-nor";
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]98 reg = <0>;
developer9b8267a2021-01-20 15:31:34 +0800[diff] [blame]99 spi-tx-bus-width = <1>;
100 spi-rx-bus-width = <4>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-all;
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]102 };
103};
104
105&uart0 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart0_pins>;
108 status = "okay";
109};
110
developerfeaa8822020-05-02 11:35:19 +0200[diff] [blame]111&xhci {
112 status = "okay";
113};
114
115&u3phy {
116 status = "okay";
117};
118
developera37ad462018-11-15 10:07:50 +0800[diff] [blame]119&watchdog {
120 pinctrl-names = "default";
121 pinctrl-0 = <&watchdog_pins>;
122 status = "okay";
123};