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git01.mediatek.com / filogic / uboot / c9c953999b6d4f728a1e9d5a9a3568925c78ef9b / . / arch / arm / dts / imx8mm-evk-u-boot.dtsi
blob: d82428f8fe8e2088751341d0043ef6a16fde2761 [file] [log] [blame]
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
12 u-boot,dm-spl;
13 };
Clement Faurea93b0d92021-03-25 17:30:33 +0800[diff] [blame]14
15 firmware {
16 optee {
17 compatible = "linaro,optee-tz";
18 method = "smc";
19 };
20 };
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]21};
22
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]23&aips4 {
24 u-boot,dm-spl;
25};
26
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]27&reg_usdhc2_vmmc {
28 u-boot,off-on-delay-us = <20000>;
29};
30
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]31&pinctrl_reg_usdhc2_vmmc {
32 u-boot,dm-spl;
33};
34
35&pinctrl_uart2 {
36 u-boot,dm-spl;
37};
38
39&pinctrl_usdhc2_gpio {
40 u-boot,dm-spl;
41};
42
43&pinctrl_usdhc2 {
44 u-boot,dm-spl;
45};
46
47&pinctrl_usdhc3 {
48 u-boot,dm-spl;
49};
50
51&gpio1 {
52 u-boot,dm-spl;
53};
54
55&gpio2 {
56 u-boot,dm-spl;
57};
58
59&gpio3 {
60 u-boot,dm-spl;
61};
62
63&gpio4 {
64 u-boot,dm-spl;
65};
66
67&gpio5 {
68 u-boot,dm-spl;
69};
70
71&uart2 {
72 u-boot,dm-spl;
73};
74
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]75&crypto {
76 u-boot,dm-spl;
77};
78
79&sec_jr0 {
80 u-boot,dm-spl;
81};
82
83&sec_jr1 {
84 u-boot,dm-spl;
85};
86
87&sec_jr2 {
88 u-boot,dm-spl;
89};
90
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]91&usbmisc1 {
92 u-boot,dm-spl;
93};
94
95&usbphynop1 {
96 u-boot,dm-spl;
97};
98
99&usbotg1 {
100 u-boot,dm-spl;
101};
102
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]103&usdhc1 {
104 u-boot,dm-spl;
105};
106
107&usdhc2 {
108 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]109 sd-uhs-sdr104;
110 sd-uhs-ddr50;
Haibo Chen26154952021-03-22 18:55:38 +0800[diff] [blame]111 fsl,signal-voltage-switch-extra-delay-ms = <8>;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]112};
113
114&usdhc3 {
115 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]116 mmc-hs400-1_8v;
117 mmc-hs400-enhanced-strobe;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]118};
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]119
120&i2c1 {
121 u-boot,dm-spl;
122};
123
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]124&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]125 u-boot,dm-spl;
126};
127
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]128&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]129 u-boot,dm-spl;
130};
131
132&pinctrl_i2c1 {
133 u-boot,dm-spl;
134};
135
136&pinctrl_pmic {
137 u-boot,dm-spl;
138};
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]139
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame]140&pinctrl_wdog {
141 u-boot,dm-spl;
142};
143
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]144&fec1 {
145 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
146};
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]147
148&wdog1 {
149 u-boot,dm-spl;
150};