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git01.mediatek.com / filogic / uboot / a279d6877de14d7d3e54b2c506f9b322a1602122 / . / arch / arm / dts / imx8mm-evk-u-boot.dtsi
blob: e9fbf7b80215011e429ca82e860f1e9649d06030 [file] [log] [blame]
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
12 u-boot,dm-spl;
13 };
Clement Faurea93b0d92021-03-25 17:30:33 +0800[diff] [blame]14
15 firmware {
16 optee {
17 compatible = "linaro,optee-tz";
18 method = "smc";
19 };
20 };
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]21};
22
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]23&reg_usdhc2_vmmc {
24 u-boot,off-on-delay-us = <20000>;
25};
26
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]27&pinctrl_reg_usdhc2_vmmc {
28 u-boot,dm-spl;
29};
30
31&pinctrl_uart2 {
32 u-boot,dm-spl;
33};
34
35&pinctrl_usdhc2_gpio {
36 u-boot,dm-spl;
37};
38
39&pinctrl_usdhc2 {
40 u-boot,dm-spl;
41};
42
43&pinctrl_usdhc3 {
44 u-boot,dm-spl;
45};
46
47&gpio1 {
48 u-boot,dm-spl;
49};
50
51&gpio2 {
52 u-boot,dm-spl;
53};
54
55&gpio3 {
56 u-boot,dm-spl;
57};
58
59&gpio4 {
60 u-boot,dm-spl;
61};
62
63&gpio5 {
64 u-boot,dm-spl;
65};
66
67&uart2 {
68 u-boot,dm-spl;
69};
70
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]71&crypto {
72 u-boot,dm-spl;
73};
74
75&sec_jr0 {
76 u-boot,dm-spl;
77};
78
79&sec_jr1 {
80 u-boot,dm-spl;
81};
82
83&sec_jr2 {
84 u-boot,dm-spl;
85};
86
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]87&usdhc1 {
88 u-boot,dm-spl;
89};
90
91&usdhc2 {
92 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]93 sd-uhs-sdr104;
94 sd-uhs-ddr50;
Haibo Chen26154952021-03-22 18:55:38 +0800[diff] [blame]95 fsl,signal-voltage-switch-extra-delay-ms = <8>;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]96};
97
98&usdhc3 {
99 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]100 mmc-hs400-1_8v;
101 mmc-hs400-enhanced-strobe;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]102};
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]103
104&i2c1 {
105 u-boot,dm-spl;
106};
107
Ye Li79e69702021-03-19 15:56:55 +0800[diff] [blame]108&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]109 u-boot,dm-spl;
110};
111
Ye Li79e69702021-03-19 15:56:55 +0800[diff] [blame]112&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]113 u-boot,dm-spl;
114};
115
116&pinctrl_i2c1 {
117 u-boot,dm-spl;
118};
119
120&pinctrl_pmic {
121 u-boot,dm-spl;
122};
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]123
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame^]124&pinctrl_wdog {
125 u-boot,dm-spl;
126};
127
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]128&fec1 {
129 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
130};
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]131
132&wdog1 {
133 u-boot,dm-spl;
134};