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git01.mediatek.com / filogic / uboot / c9c54e2f603766d549bd4e94b011e234f915fe15 / . / board / sacsng / clkinit.c
blob: 2a28037dc3da4e18ae0bebbf3a38a0a5908bc0fb [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Jon Diekema <diekema@cideas.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]7 */
8
9#include <common.h>
10#include <ioports.h>
11#include <mpc8260.h>
12#include <asm/cpm_8260.h>
13#include <configs/sacsng.h>
14
15#include "clkinit.h"
16
Wolfgang Denk6405a152006-03-31 18:32:53 +0200[diff] [blame]17DECLARE_GLOBAL_DATA_PTR;
18
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]19int Daq64xSampling = 0;
20
21
22void Daq_BRG_Reset(uint brg)
23{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]24 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]25 volatile uint *brg_ptr;
26
27 brg_ptr = (uint *)&immr->im_brgc1;
28
29 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]30 brg_ptr = (uint *)&immr->im_brgc5;
31 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]32 }
33 brg_ptr += brg;
34 *brg_ptr |= CPM_BRG_RST;
35 *brg_ptr &= ~CPM_BRG_RST;
36}
37
38void Daq_BRG_Disable(uint brg)
39{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]40 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]41 volatile uint *brg_ptr;
42
43 brg_ptr = (uint *)&immr->im_brgc1;
44
45 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]46 brg_ptr = (uint *)&immr->im_brgc5;
47 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]48 }
49 brg_ptr += brg;
50 *brg_ptr &= ~CPM_BRG_EN;
51}
52
53void Daq_BRG_Enable(uint brg)
54{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]55 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]56 volatile uint *brg_ptr;
57
58 brg_ptr = (uint *)&immr->im_brgc1;
59 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]60 brg_ptr = (uint *)&immr->im_brgc5;
61 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]62 }
63 brg_ptr += brg;
64 *brg_ptr |= CPM_BRG_EN;
65}
66
67uint Daq_BRG_Get_Div16(uint brg)
68{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]69 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]70 uint *brg_ptr;
71
72 brg_ptr = (uint *)&immr->im_brgc1;
73 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]74 brg_ptr = (uint *)&immr->im_brgc5;
75 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]76 }
77 brg_ptr += brg;
78
79 if (*brg_ptr & CPM_BRG_DIV16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]80 /* DIV16 active */
York Sun4a598092013-04-01 11:29:11 -0700[diff] [blame]81 return true;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]82 }
83 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]84 /* DIV16 inactive */
York Sun4a598092013-04-01 11:29:11 -0700[diff] [blame]85 return false;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]86 }
87}
88
89void Daq_BRG_Set_Div16(uint brg, uint div16)
90{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]91 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]92 uint *brg_ptr;
93
94 brg_ptr = (uint *)&immr->im_brgc1;
95 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]96 brg_ptr = (uint *)&immr->im_brgc5;
97 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]98 }
99 brg_ptr += brg;
100
101 if (div16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]102 /* DIV16 active */
103 *brg_ptr |= CPM_BRG_DIV16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]104 }
105 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]106 /* DIV16 inactive */
107 *brg_ptr &= ~CPM_BRG_DIV16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]108 }
109}
110
111uint Daq_BRG_Get_Count(uint brg)
112{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]113 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]114 uint *brg_ptr;
115 uint brg_cnt;
116
117 brg_ptr = (uint *)&immr->im_brgc1;
118 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]119 brg_ptr = (uint *)&immr->im_brgc5;
120 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]121 }
122 brg_ptr += brg;
123
124 /* Get the clock divider
125 *
126 * Note: A clock divider of 0 means divide by 1,
127 * therefore we need to add 1 to the count.
128 */
129 brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
130 brg_cnt++;
131 if (*brg_ptr & CPM_BRG_DIV16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]132 brg_cnt *= 16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]133 }
134
135 return (brg_cnt);
136}
137
138void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
139{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]140 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]141 uint *brg_ptr;
142
143 brg_ptr = (uint *)&immr->im_brgc1;
144 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]145 brg_ptr = (uint *)&immr->im_brgc5;
146 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]147 }
148 brg_ptr += brg;
149
150 /*
151 * Note: A clock divider of 0 means divide by 1,
152 * therefore we need to subtract 1 from the count.
153 */
154 if (brg_cnt > 4096) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]155 /* Prescale = Divide by 16 */
156 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]157 (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
158 *brg_ptr |= CPM_BRG_DIV16;
159 }
160 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]161 /* Prescale = Divide by 1 */
162 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]163 ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
164 *brg_ptr &= ~CPM_BRG_DIV16;
165 }
166}
167
168uint Daq_BRG_Get_ExtClk(uint brg)
169{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]170 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]171 uint *brg_ptr;
172
173 brg_ptr = (uint *)&immr->im_brgc1;
174 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]175 brg_ptr = (uint *)&immr->im_brgc5;
176 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]177 }
178 brg_ptr += brg;
179
180 return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
181}
182
183char* Daq_BRG_Get_ExtClk_Description(uint brg)
184{
185 uint extc;
186
187 extc = Daq_BRG_Get_ExtClk(brg);
188
189 switch (brg + 1) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]190 case 1:
191 case 2:
192 case 5:
193 case 6: {
194 switch (extc) {
195 case 0: {
196 return ("BRG_INT");
197 }
198 case 1: {
199 return ("CLK3");
200 }
201 case 2: {
202 return ("CLK5");
203 }
204 }
205 return ("??1245??");
206 }
207 case 3:
208 case 4:
209 case 7:
210 case 8: {
211 switch (extc) {
212 case 0: {
213 return ("BRG_INT");
214 }
215 case 1: {
216 return ("CLK9");
217 }
218 case 2: {
219 return ("CLK15");
220 }
221 }
222 return ("??3478??");
223 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]224 }
225 return ("??9876??");
226}
227
228void Daq_BRG_Set_ExtClk(uint brg, uint extc)
229{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]230 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]231 uint *brg_ptr;
232
233 brg_ptr = (uint *)&immr->im_brgc1;
234 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]235 brg_ptr = (uint *)&immr->im_brgc5;
236 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]237 }
238 brg_ptr += brg;
239
240 *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]241 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]242}
243
244uint Daq_BRG_Rate(uint brg)
245{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]246 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]247 uint *brg_ptr;
248 uint brg_cnt;
249 uint brg_freq = 0;
250
251 brg_ptr = (uint *)&immr->im_brgc1;
252 brg_ptr += brg;
253 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]254 brg_ptr = (uint *)&immr->im_brgc5;
255 brg_ptr += (brg - 4);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]256 }
257
258 brg_cnt = Daq_BRG_Get_Count(brg);
259
260 switch (Daq_BRG_Get_ExtClk(brg)) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]261 case CPM_BRG_EXTC_CLK3:
262 case CPM_BRG_EXTC_CLK5: {
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]263 brg_freq = brg_cnt;
264 break;
265 }
266 default: {
267 brg_freq = (uint)BRG_INT_CLK / brg_cnt;
268 }
269 }
270 return (brg_freq);
271}
272
273uint Daq_Get_SampleRate(void)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]274{
275 /*
276 * Read the BRG's to return the actual sample rate.
277 */
278 return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
279}
280
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]281void Daq_Init_Clocks(int sample_rate, int sample_64x)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]282{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]283 volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]284 uint mclk_divisor; /* MCLK divisor */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]285 int flag; /* Interrupt state */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]286
287 /* Save off the clocking data */
288 Daq64xSampling = sample_64x;
289
290 /*
291 * Limit the sample rate to some sensible values.
292 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]293 if (sample_rate > MAX_64x_SAMPLE_RATE) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]294 sample_rate = MAX_64x_SAMPLE_RATE;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]295 }
296 if (sample_rate < MIN_SAMPLE_RATE) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]297 sample_rate = MIN_SAMPLE_RATE;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]298 }
299
300 /*
301 * Initialize the MCLK/SCLK/LRCLK baud rate generators.
302 */
303
304 /* Setup MCLK */
305 Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
306
307 /* Setup SCLK */
308# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]309 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]310# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]311 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]312# endif
313
314 /* Setup LRCLK */
315# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]316 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]317# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]318 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]319# endif
320
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]321 /*
322 * Dynamically adjust MCLK based on the new sample rate.
323 */
324
325 /* Compute the divisors */
326 mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
327
328 /*
329 * Disable interrupt and save the current state
330 */
331 flag = disable_interrupts();
332
333 /* Setup MCLK */
334 Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
335
336 /* Setup SCLK */
337# ifdef RUN_SCLK_ON_BRG_INT
338 Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
339# else
340 Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
341# endif
342
343# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]344 Daq_BRG_Set_Count(LRCLK_BRG,
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]345 mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
346# else
347 Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
348# endif
349
350 /*
351 * Restore the Interrupt state
352 */
353 if (flag) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]354 enable_interrupts();
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]355 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]356
357 /* Enable the clock drivers */
358 iopa->pdat &= ~SLRCLK_EN_MASK;
359}
360
361void Daq_Stop_Clocks(void)
362
363{
364#ifdef TIGHTEN_UP_BRG_TIMING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]365 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]366 register uint mclk_brg; /* MCLK BRG value */
367 register uint sclk_brg; /* SCLK BRG value */
368 register uint lrclk_brg; /* LRCLK BRG value */
369 unsigned long flag; /* Interrupt flags */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]370#endif
371
372# ifdef TIGHTEN_UP_BRG_TIMING
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]373 /*
374 * Obtain MCLK BRG reset/disabled value
375 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]376# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]377 mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]378# endif
379# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]380 mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]381# endif
382# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]383 mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]384# endif
385# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]386 mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]387# endif
388# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]389 mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]390# endif
391# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]392 mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]393# endif
394# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]395 mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]396# endif
397# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]398 mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]399# endif
400
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]401 /*
402 * Obtain SCLK BRG reset/disabled value
403 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]404# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]405 sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]406# endif
407# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]408 sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]409# endif
410# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]411 sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]412# endif
413# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]414 sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]415# endif
416# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]417 sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]418# endif
419# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]420 sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]421# endif
422# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]423 sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]424# endif
425# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]426 sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]427# endif
428
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]429 /*
430 * Obtain LRCLK BRG reset/disabled value
431 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]432# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]433 lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]434# endif
435# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]436 lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]437# endif
438# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]439 lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]440# endif
441# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]442 lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]443# endif
444# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]445 lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]446# endif
447# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]448 lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]449# endif
450# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]451 lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]452# endif
453# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]454 lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]455# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]456
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]457 /*
458 * Disable interrupt and save the current state
459 */
460 flag = disable_interrupts();
461
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]462 /*
463 * Set reset on MCLK BRG
464 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]465# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]466 *IM_BRGC1 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]467# endif
468# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]469 *IM_BRGC2 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]470# endif
471# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]472 *IM_BRGC3 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]473# endif
474# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]475 *IM_BRGC4 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]476# endif
477# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]478 *IM_BRGC5 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]479# endif
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]480# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]481 *IM_BRGC6 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]482# endif
483# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]484 *IM_BRGC7 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]485# endif
486# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]487 *IM_BRGC8 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]488# endif
489
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]490 /*
491 * Set reset on SCLK BRG
492 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]493# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]494 *IM_BRGC1 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]495# endif
496# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]497 *IM_BRGC2 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]498# endif
499# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]500 *IM_BRGC3 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]501# endif
502# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]503 *IM_BRGC4 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]504# endif
505# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]506 *IM_BRGC5 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]507# endif
508# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]509 *IM_BRGC6 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]510# endif
511# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]512 *IM_BRGC7 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]513# endif
514# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]515 *IM_BRGC8 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]516# endif
517
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]518 /*
519 * Set reset on LRCLK BRG
520 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]521# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]522 *IM_BRGC1 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]523# endif
524# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]525 *IM_BRGC2 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]526# endif
527# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]528 *IM_BRGC3 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]529# endif
530# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]531 *IM_BRGC4 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]532# endif
533# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]534 *IM_BRGC5 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]535# endif
536# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]537 *IM_BRGC6 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]538# endif
539# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]540 *IM_BRGC7 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]541# endif
542# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]543 *IM_BRGC8 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]544# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]545
546 /*
547 * Clear reset on MCLK BRG
548 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]549# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]550 *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]551# endif
552# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]553 *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]554# endif
555# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]556 *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]557# endif
558# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]559 *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]560# endif
561# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]562 *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]563# endif
564# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]565 *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]566# endif
567# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]568 *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]569# endif
570# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]571 *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]572# endif
573
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]574 /*
575 * Clear reset on SCLK BRG
576 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]577# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]578 *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]579# endif
580# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]581 *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]582# endif
583# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]584 *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]585# endif
586# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]587 *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]588# endif
589# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]590 *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]591# endif
592# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]593 *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]594# endif
595# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]596 *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]597# endif
598# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]599 *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]600# endif
601
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]602 /*
603 * Clear reset on LRCLK BRG
604 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]605# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]606 *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]607# endif
608# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]609 *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]610# endif
611# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]612 *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]613# endif
614# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]615 *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]616# endif
617# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]618 *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]619# endif
620# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]621 *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]622# endif
623# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]624 *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]625# endif
626# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]627 *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]628# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]629
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]630 /*
631 * Restore the Interrupt state
632 */
633 if (flag) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]634 enable_interrupts();
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]635 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]636# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]637 /*
638 * Reset the clocks
639 */
640 Daq_BRG_Reset(MCLK_BRG);
641 Daq_BRG_Reset(SCLK_BRG);
642 Daq_BRG_Reset(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]643# endif
644}
645
646void Daq_Start_Clocks(int sample_rate)
647
648{
649#ifdef TIGHTEN_UP_BRG_TIMING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]650 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]651
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]652 register uint mclk_brg; /* MCLK BRG value */
653 register uint sclk_brg; /* SCLK BRG value */
654 register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
655 register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]656 uint lrclk_brg; /* LRCLK BRG value */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]657 unsigned long flags; /* Interrupt flags */
658 uint sclk_cnt; /* SCLK count */
659 uint delay_cnt; /* Delay count */
660#endif
661
662# ifdef TIGHTEN_UP_BRG_TIMING
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]663 /*
664 * Obtain the enabled MCLK BRG value
665 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]666# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]667 mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]668# endif
669# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]670 mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]671# endif
672# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]673 mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]674# endif
675# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]676 mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]677# endif
678# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]679 mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]680# endif
681# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]682 mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]683# endif
684# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]685 mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]686# endif
687# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]688 mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]689# endif
690
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]691 /*
692 * Obtain the enabled SCLK BRG value
693 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]694# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]695 sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]696# endif
697# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]698 sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]699# endif
700# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]701 sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]702# endif
703# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]704 sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]705# endif
706# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]707 sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]708# endif
709# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]710 sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]711# endif
712# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]713 sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]714# endif
715# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]716 sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]717# endif
718
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]719 /*
720 * Obtain the enabled LRCLK BRG value
721 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]722# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]723 lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]724# endif
725# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]726 lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]727# endif
728# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]729 lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]730# endif
731# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]732 lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]733# endif
734# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]735 lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]736# endif
737# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]738 lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]739# endif
740# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]741 lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]742# endif
743# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]744 lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]745# endif
746
747 /* Save off the real LRCLK value */
748 real_lrclk_brg = lrclk_brg;
749
750 /* Obtain the current SCLK count */
751 sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
752
753 /* Compute the delay as a function of SCLK count */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]754 delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]755 if (DaqSampleRate == 43402) {
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]756 delay_cnt++;
757 }
758
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]759 /* Clear out the count */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]760 temp_lrclk_brg = sclk_brg & ~0x00001FFE;
761
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]762 /* Insert the count */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]763 temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
764
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]765 /*
766 * Disable interrupt and save the current state
767 */
768 flag = disable_interrupts();
769
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]770 /*
771 * Enable MCLK BRG
772 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]773# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]774 *IM_BRGC1 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]775# endif
776# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]777 *IM_BRGC2 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]778# endif
779# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]780 *IM_BRGC3 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]781# endif
782# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]783 *IM_BRGC4 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]784# endif
785# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]786 *IM_BRGC5 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]787# endif
788# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]789 *IM_BRGC6 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]790# endif
791# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]792 *IM_BRGC7 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]793# endif
794# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]795 *IM_BRGC8 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]796# endif
797
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]798 /*
799 * Enable SCLK BRG
800 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]801# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]802 *IM_BRGC1 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]803# endif
804# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]805 *IM_BRGC2 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]806# endif
807# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]808 *IM_BRGC3 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]809# endif
810# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]811 *IM_BRGC4 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]812# endif
813# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]814 *IM_BRGC5 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]815# endif
816# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]817 *IM_BRGC6 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]818# endif
819# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]820 *IM_BRGC7 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]821# endif
822# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]823 *IM_BRGC8 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]824# endif
825
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]826 /*
827 * Enable LRCLK BRG (1st time - temporary)
828 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]829# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]830 *IM_BRGC1 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]831# endif
832# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]833 *IM_BRGC2 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]834# endif
835# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]836 *IM_BRGC3 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]837# endif
838# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]839 *IM_BRGC4 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]840# endif
841# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]842 *IM_BRGC5 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]843# endif
844# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]845 *IM_BRGC6 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]846# endif
847# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]848 *IM_BRGC7 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]849# endif
850# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]851 *IM_BRGC8 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]852# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]853
854 /*
855 * Enable LRCLK BRG (2nd time - permanent)
856 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]857# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]858 *IM_BRGC1 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]859# endif
860# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]861 *IM_BRGC2 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]862# endif
863# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]864 *IM_BRGC3 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]865# endif
866# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]867 *IM_BRGC4 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]868# endif
869# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]870 *IM_BRGC5 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]871# endif
872# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]873 *IM_BRGC6 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]874# endif
875# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]876 *IM_BRGC7 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]877# endif
878# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]879 *IM_BRGC8 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]880# endif
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]881
882 /*
883 * Restore the Interrupt state
884 */
885 if (flag) {
886 enable_interrupts();
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]887 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]888# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]889 /*
890 * Enable the clocks
891 */
892 Daq_BRG_Enable(LRCLK_BRG);
893 Daq_BRG_Enable(SCLK_BRG);
894 Daq_BRG_Enable(MCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]895# endif
896}
897
898void Daq_Display_Clocks(void)
899
900{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]901 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]902 uint mclk_divisor; /* Detected MCLK divisor */
903 uint sclk_divisor; /* Detected SCLK divisor */
904
905 printf("\nBRG:\n");
906 if (immr->im_brgc4 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]907 printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]908 immr->im_brgc4,
909 (uint)&(immr->im_brgc4),
910 Daq_BRG_Get_Count(3),
911 Daq_BRG_Get_ExtClk(3),
912 Daq_BRG_Get_ExtClk_Description(3));
913 }
914 if (immr->im_brgc8 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]915 printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]916 immr->im_brgc8,
917 (uint)&(immr->im_brgc8),
918 Daq_BRG_Get_Count(7),
919 Daq_BRG_Get_ExtClk(7),
920 Daq_BRG_Get_ExtClk_Description(7));
921 }
922 if (immr->im_brgc6 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]923 printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]924 immr->im_brgc6,
925 (uint)&(immr->im_brgc6),
926 Daq_BRG_Get_Count(5),
927 Daq_BRG_Get_ExtClk(5),
928 Daq_BRG_Get_ExtClk_Description(5));
929 }
930 if (immr->im_brgc1 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]931 printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]932 immr->im_brgc1,
933 (uint)&(immr->im_brgc1),
934 Daq_BRG_Get_Count(0),
935 Daq_BRG_Get_ExtClk(0),
936 Daq_BRG_Get_ExtClk_Description(0));
937 }
938 if (immr->im_brgc2 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]939 printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]940 immr->im_brgc2,
941 (uint)&(immr->im_brgc2),
942 Daq_BRG_Get_Count(1),
943 Daq_BRG_Get_ExtClk(1),
944 Daq_BRG_Get_ExtClk_Description(1));
945 }
946 if (immr->im_brgc3 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]947 printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]948 immr->im_brgc3,
949 (uint)&(immr->im_brgc3),
950 Daq_BRG_Get_Count(2),
951 Daq_BRG_Get_ExtClk(2),
952 Daq_BRG_Get_ExtClk_Description(2));
953 }
954 if (immr->im_brgc5 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]955 printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]956 immr->im_brgc5,
957 (uint)&(immr->im_brgc5),
958 Daq_BRG_Get_Count(4),
959 Daq_BRG_Get_ExtClk(4),
960 Daq_BRG_Get_ExtClk_Description(4));
961 }
962 if (immr->im_brgc7 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]963 printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]964 immr->im_brgc7,
965 (uint)&(immr->im_brgc7),
966 Daq_BRG_Get_Count(6),
967 Daq_BRG_Get_ExtClk(6),
968 Daq_BRG_Get_ExtClk_Description(6));
969 }
970
971# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]972 mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]973# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]974 mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]975# endif
976# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]977 sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]978# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]979 sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]980# endif
981
982 printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
983 printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
984 Daq_BRG_Rate(MCLK_BRG),
985 mclk_divisor,
986 mclk_divisor * sclk_divisor);
987# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]988 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]989 Daq_BRG_Rate(SCLK_BRG),
990 sclk_divisor);
991# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]992 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]993 Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
994 sclk_divisor);
995# endif
996# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]997 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]998 Daq_BRG_Rate(LRCLK_BRG));
999# else
1000# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]1001 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1002 Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1003# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]1004 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1005 Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
1006# endif
1007# endif
1008 printf("\n");
1009}