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git01.mediatek.com / filogic / uboot / 57b2d80d02a93a4d491604e14575c0a7e1eb6fbc / . / board / sacsng / clkinit.c
blob: ea4c65d6b34fb007b7a6a42c7611b4cea0f95eea [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Jon Diekema <diekema@cideas.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <ioports.h>
27#include <mpc8260.h>
28#include <asm/cpm_8260.h>
29#include <configs/sacsng.h>
30
31#include "clkinit.h"
32
33int Daq64xSampling = 0;
34
35
36void Daq_BRG_Reset(uint brg)
37{
38 volatile immap_t *immr = (immap_t *)CFG_IMMR;
39 volatile uint *brg_ptr;
40
41 brg_ptr = (uint *)&immr->im_brgc1;
42
43 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]44 brg_ptr = (uint *)&immr->im_brgc5;
45 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]46 }
47 brg_ptr += brg;
48 *brg_ptr |= CPM_BRG_RST;
49 *brg_ptr &= ~CPM_BRG_RST;
50}
51
52void Daq_BRG_Disable(uint brg)
53{
54 volatile immap_t *immr = (immap_t *)CFG_IMMR;
55 volatile uint *brg_ptr;
56
57 brg_ptr = (uint *)&immr->im_brgc1;
58
59 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]60 brg_ptr = (uint *)&immr->im_brgc5;
61 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]62 }
63 brg_ptr += brg;
64 *brg_ptr &= ~CPM_BRG_EN;
65}
66
67void Daq_BRG_Enable(uint brg)
68{
69 volatile immap_t *immr = (immap_t *)CFG_IMMR;
70 volatile uint *brg_ptr;
71
72 brg_ptr = (uint *)&immr->im_brgc1;
73 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]74 brg_ptr = (uint *)&immr->im_brgc5;
75 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]76 }
77 brg_ptr += brg;
78 *brg_ptr |= CPM_BRG_EN;
79}
80
81uint Daq_BRG_Get_Div16(uint brg)
82{
83 volatile immap_t *immr = (immap_t *)CFG_IMMR;
84 uint *brg_ptr;
85
86 brg_ptr = (uint *)&immr->im_brgc1;
87 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]88 brg_ptr = (uint *)&immr->im_brgc5;
89 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]90 }
91 brg_ptr += brg;
92
93 if (*brg_ptr & CPM_BRG_DIV16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]94 /* DIV16 active */
95 return (TRUE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]96 }
97 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]98 /* DIV16 inactive */
99 return (FALSE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]100 }
101}
102
103void Daq_BRG_Set_Div16(uint brg, uint div16)
104{
105 volatile immap_t *immr = (immap_t *)CFG_IMMR;
106 uint *brg_ptr;
107
108 brg_ptr = (uint *)&immr->im_brgc1;
109 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]110 brg_ptr = (uint *)&immr->im_brgc5;
111 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]112 }
113 brg_ptr += brg;
114
115 if (div16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]116 /* DIV16 active */
117 *brg_ptr |= CPM_BRG_DIV16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]118 }
119 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]120 /* DIV16 inactive */
121 *brg_ptr &= ~CPM_BRG_DIV16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]122 }
123}
124
125uint Daq_BRG_Get_Count(uint brg)
126{
127 volatile immap_t *immr = (immap_t *)CFG_IMMR;
128 uint *brg_ptr;
129 uint brg_cnt;
130
131 brg_ptr = (uint *)&immr->im_brgc1;
132 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]133 brg_ptr = (uint *)&immr->im_brgc5;
134 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]135 }
136 brg_ptr += brg;
137
138 /* Get the clock divider
139 *
140 * Note: A clock divider of 0 means divide by 1,
141 * therefore we need to add 1 to the count.
142 */
143 brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
144 brg_cnt++;
145 if (*brg_ptr & CPM_BRG_DIV16) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]146 brg_cnt *= 16;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]147 }
148
149 return (brg_cnt);
150}
151
152void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
153{
154 volatile immap_t *immr = (immap_t *)CFG_IMMR;
155 uint *brg_ptr;
156
157 brg_ptr = (uint *)&immr->im_brgc1;
158 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]159 brg_ptr = (uint *)&immr->im_brgc5;
160 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]161 }
162 brg_ptr += brg;
163
164 /*
165 * Note: A clock divider of 0 means divide by 1,
166 * therefore we need to subtract 1 from the count.
167 */
168 if (brg_cnt > 4096) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]169 /* Prescale = Divide by 16 */
170 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]171 (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
172 *brg_ptr |= CPM_BRG_DIV16;
173 }
174 else {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]175 /* Prescale = Divide by 1 */
176 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]177 ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
178 *brg_ptr &= ~CPM_BRG_DIV16;
179 }
180}
181
182uint Daq_BRG_Get_ExtClk(uint brg)
183{
184 volatile immap_t *immr = (immap_t *)CFG_IMMR;
185 uint *brg_ptr;
186
187 brg_ptr = (uint *)&immr->im_brgc1;
188 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]189 brg_ptr = (uint *)&immr->im_brgc5;
190 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]191 }
192 brg_ptr += brg;
193
194 return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
195}
196
197char* Daq_BRG_Get_ExtClk_Description(uint brg)
198{
199 uint extc;
200
201 extc = Daq_BRG_Get_ExtClk(brg);
202
203 switch (brg + 1) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]204 case 1:
205 case 2:
206 case 5:
207 case 6: {
208 switch (extc) {
209 case 0: {
210 return ("BRG_INT");
211 }
212 case 1: {
213 return ("CLK3");
214 }
215 case 2: {
216 return ("CLK5");
217 }
218 }
219 return ("??1245??");
220 }
221 case 3:
222 case 4:
223 case 7:
224 case 8: {
225 switch (extc) {
226 case 0: {
227 return ("BRG_INT");
228 }
229 case 1: {
230 return ("CLK9");
231 }
232 case 2: {
233 return ("CLK15");
234 }
235 }
236 return ("??3478??");
237 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]238 }
239 return ("??9876??");
240}
241
242void Daq_BRG_Set_ExtClk(uint brg, uint extc)
243{
244 volatile immap_t *immr = (immap_t *)CFG_IMMR;
245 uint *brg_ptr;
246
247 brg_ptr = (uint *)&immr->im_brgc1;
248 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]249 brg_ptr = (uint *)&immr->im_brgc5;
250 brg -= 4;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]251 }
252 brg_ptr += brg;
253
254 *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]255 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]256}
257
258uint Daq_BRG_Rate(uint brg)
259{
260 DECLARE_GLOBAL_DATA_PTR;
261 volatile immap_t *immr = (immap_t *)CFG_IMMR;
262 uint *brg_ptr;
263 uint brg_cnt;
264 uint brg_freq = 0;
265
266 brg_ptr = (uint *)&immr->im_brgc1;
267 brg_ptr += brg;
268 if (brg >= 5) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]269 brg_ptr = (uint *)&immr->im_brgc5;
270 brg_ptr += (brg - 4);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]271 }
272
273 brg_cnt = Daq_BRG_Get_Count(brg);
274
275 switch (Daq_BRG_Get_ExtClk(brg)) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]276 case CPM_BRG_EXTC_CLK3:
277 case CPM_BRG_EXTC_CLK5: {
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]278 brg_freq = brg_cnt;
279 break;
280 }
281 default: {
282 brg_freq = (uint)BRG_INT_CLK / brg_cnt;
283 }
284 }
285 return (brg_freq);
286}
287
288uint Daq_Get_SampleRate(void)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]289{
290 /*
291 * Read the BRG's to return the actual sample rate.
292 */
293 return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
294}
295
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]296void Daq_Init_Clocks(int sample_rate, int sample_64x)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]297{
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]298 DECLARE_GLOBAL_DATA_PTR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]299 volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]300 uint mclk_divisor; /* MCLK divisor */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]301 int flag; /* Interrupt state */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]302
303 /* Save off the clocking data */
304 Daq64xSampling = sample_64x;
305
306 /*
307 * Limit the sample rate to some sensible values.
308 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]309 if (sample_rate > MAX_64x_SAMPLE_RATE) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]310 sample_rate = MAX_64x_SAMPLE_RATE;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]311 }
312 if (sample_rate < MIN_SAMPLE_RATE) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]313 sample_rate = MIN_SAMPLE_RATE;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]314 }
315
316 /*
317 * Initialize the MCLK/SCLK/LRCLK baud rate generators.
318 */
319
320 /* Setup MCLK */
321 Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
322
323 /* Setup SCLK */
324# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]325 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]326# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]327 Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]328# endif
329
330 /* Setup LRCLK */
331# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]332 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]333# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]334 Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]335# endif
336
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]337 /*
338 * Dynamically adjust MCLK based on the new sample rate.
339 */
340
341 /* Compute the divisors */
342 mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
343
344 /*
345 * Disable interrupt and save the current state
346 */
347 flag = disable_interrupts();
348
349 /* Setup MCLK */
350 Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
351
352 /* Setup SCLK */
353# ifdef RUN_SCLK_ON_BRG_INT
354 Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
355# else
356 Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
357# endif
358
359# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]360 Daq_BRG_Set_Count(LRCLK_BRG,
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]361 mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
362# else
363 Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
364# endif
365
366 /*
367 * Restore the Interrupt state
368 */
369 if (flag) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]370 enable_interrupts();
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]371 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]372
373 /* Enable the clock drivers */
374 iopa->pdat &= ~SLRCLK_EN_MASK;
375}
376
377void Daq_Stop_Clocks(void)
378
379{
380#ifdef TIGHTEN_UP_BRG_TIMING
381 volatile immap_t *immr = (immap_t *)CFG_IMMR;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]382 register uint mclk_brg; /* MCLK BRG value */
383 register uint sclk_brg; /* SCLK BRG value */
384 register uint lrclk_brg; /* LRCLK BRG value */
385 unsigned long flag; /* Interrupt flags */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]386#endif
387
388# ifdef TIGHTEN_UP_BRG_TIMING
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]389 /*
390 * Obtain MCLK BRG reset/disabled value
391 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]392# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]393 mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]394# endif
395# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]396 mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]397# endif
398# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]399 mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]400# endif
401# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]402 mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]403# endif
404# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]405 mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]406# endif
407# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]408 mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]409# endif
410# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]411 mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]412# endif
413# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]414 mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]415# endif
416
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]417 /*
418 * Obtain SCLK BRG reset/disabled value
419 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]420# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]421 sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]422# endif
423# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]424 sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]425# endif
426# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]427 sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]428# endif
429# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]430 sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]431# endif
432# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]433 sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]434# endif
435# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]436 sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]437# endif
438# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]439 sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]440# endif
441# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]442 sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]443# endif
444
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]445 /*
446 * Obtain LRCLK BRG reset/disabled value
447 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]448# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]449 lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]450# endif
451# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]452 lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]453# endif
454# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]455 lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]456# endif
457# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]458 lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]459# endif
460# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]461 lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]462# endif
463# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]464 lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]465# endif
466# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]467 lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]468# endif
469# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]470 lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]471# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]472
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]473 /*
474 * Disable interrupt and save the current state
475 */
476 flag = disable_interrupts();
477
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]478 /*
479 * Set reset on MCLK BRG
480 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]481# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]482 *IM_BRGC1 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]483# endif
484# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]485 *IM_BRGC2 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]486# endif
487# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]488 *IM_BRGC3 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]489# endif
490# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]491 *IM_BRGC4 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]492# endif
493# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]494 *IM_BRGC5 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]495# endif
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]496# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]497 *IM_BRGC6 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]498# endif
499# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]500 *IM_BRGC7 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]501# endif
502# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]503 *IM_BRGC8 = mclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]504# endif
505
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]506 /*
507 * Set reset on SCLK BRG
508 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]509# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]510 *IM_BRGC1 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]511# endif
512# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]513 *IM_BRGC2 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]514# endif
515# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]516 *IM_BRGC3 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]517# endif
518# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]519 *IM_BRGC4 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]520# endif
521# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]522 *IM_BRGC5 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]523# endif
524# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]525 *IM_BRGC6 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]526# endif
527# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]528 *IM_BRGC7 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]529# endif
530# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]531 *IM_BRGC8 = sclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]532# endif
533
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]534 /*
535 * Set reset on LRCLK BRG
536 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]537# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]538 *IM_BRGC1 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]539# endif
540# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]541 *IM_BRGC2 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]542# endif
543# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]544 *IM_BRGC3 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]545# endif
546# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]547 *IM_BRGC4 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]548# endif
549# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]550 *IM_BRGC5 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]551# endif
552# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]553 *IM_BRGC6 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]554# endif
555# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]556 *IM_BRGC7 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]557# endif
558# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]559 *IM_BRGC8 = lrclk_brg;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]560# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]561
562 /*
563 * Clear reset on MCLK BRG
564 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]565# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]566 *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]567# endif
568# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]569 *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]570# endif
571# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]572 *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]573# endif
574# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]575 *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]576# endif
577# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]578 *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]579# endif
580# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]581 *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]582# endif
583# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]584 *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]585# endif
586# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]587 *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]588# endif
589
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]590 /*
591 * Clear reset on SCLK BRG
592 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]593# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]594 *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]595# endif
596# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]597 *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]598# endif
599# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]600 *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]601# endif
602# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]603 *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]604# endif
605# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]606 *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]607# endif
608# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]609 *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]610# endif
611# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]612 *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]613# endif
614# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]615 *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]616# endif
617
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]618 /*
619 * Clear reset on LRCLK BRG
620 */
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]621# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]622 *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]623# endif
624# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]625 *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]626# endif
627# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]628 *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]629# endif
630# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]631 *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]632# endif
633# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]634 *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]635# endif
636# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]637 *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]638# endif
639# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]640 *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]641# endif
642# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]643 *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]644# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]645
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]646 /*
647 * Restore the Interrupt state
648 */
649 if (flag) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]650 enable_interrupts();
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]651 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]652# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]653 /*
654 * Reset the clocks
655 */
656 Daq_BRG_Reset(MCLK_BRG);
657 Daq_BRG_Reset(SCLK_BRG);
658 Daq_BRG_Reset(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]659# endif
660}
661
662void Daq_Start_Clocks(int sample_rate)
663
664{
665#ifdef TIGHTEN_UP_BRG_TIMING
666 volatile immap_t *immr = (immap_t *)CFG_IMMR;
667
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]668 register uint mclk_brg; /* MCLK BRG value */
669 register uint sclk_brg; /* SCLK BRG value */
670 register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
671 register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]672 uint lrclk_brg; /* LRCLK BRG value */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]673 unsigned long flags; /* Interrupt flags */
674 uint sclk_cnt; /* SCLK count */
675 uint delay_cnt; /* Delay count */
676#endif
677
678# ifdef TIGHTEN_UP_BRG_TIMING
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]679 /*
680 * Obtain the enabled MCLK BRG value
681 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]682# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]683 mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]684# endif
685# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]686 mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]687# endif
688# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]689 mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]690# endif
691# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]692 mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]693# endif
694# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]695 mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]696# endif
697# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]698 mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]699# endif
700# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]701 mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]702# endif
703# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]704 mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]705# endif
706
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]707 /*
708 * Obtain the enabled SCLK BRG value
709 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]710# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]711 sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]712# endif
713# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]714 sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]715# endif
716# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]717 sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]718# endif
719# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]720 sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]721# endif
722# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]723 sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]724# endif
725# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]726 sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]727# endif
728# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]729 sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]730# endif
731# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]732 sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]733# endif
734
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]735 /*
736 * Obtain the enabled LRCLK BRG value
737 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]738# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]739 lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]740# endif
741# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]742 lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]743# endif
744# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]745 lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]746# endif
747# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]748 lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]749# endif
750# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]751 lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]752# endif
753# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]754 lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]755# endif
756# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]757 lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]758# endif
759# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]760 lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]761# endif
762
763 /* Save off the real LRCLK value */
764 real_lrclk_brg = lrclk_brg;
765
766 /* Obtain the current SCLK count */
767 sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
768
769 /* Compute the delay as a function of SCLK count */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]770 delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]771 if (DaqSampleRate == 43402) {
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]772 delay_cnt++;
773 }
774
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]775 /* Clear out the count */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]776 temp_lrclk_brg = sclk_brg & ~0x00001FFE;
777
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]778 /* Insert the count */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]779 temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
780
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]781 /*
782 * Disable interrupt and save the current state
783 */
784 flag = disable_interrupts();
785
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]786 /*
787 * Enable MCLK BRG
788 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]789# if (MCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]790 *IM_BRGC1 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]791# endif
792# if (MCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]793 *IM_BRGC2 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]794# endif
795# if (MCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]796 *IM_BRGC3 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]797# endif
798# if (MCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]799 *IM_BRGC4 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]800# endif
801# if (MCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]802 *IM_BRGC5 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]803# endif
804# if (MCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]805 *IM_BRGC6 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]806# endif
807# if (MCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]808 *IM_BRGC7 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]809# endif
810# if (MCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]811 *IM_BRGC8 = mclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]812# endif
813
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]814 /*
815 * Enable SCLK BRG
816 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]817# if (SCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]818 *IM_BRGC1 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]819# endif
820# if (SCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]821 *IM_BRGC2 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]822# endif
823# if (SCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]824 *IM_BRGC3 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]825# endif
826# if (SCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]827 *IM_BRGC4 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]828# endif
829# if (SCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]830 *IM_BRGC5 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]831# endif
832# if (SCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]833 *IM_BRGC6 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]834# endif
835# if (SCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]836 *IM_BRGC7 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]837# endif
838# if (SCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]839 *IM_BRGC8 = sclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]840# endif
841
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]842 /*
843 * Enable LRCLK BRG (1st time - temporary)
844 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]845# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]846 *IM_BRGC1 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]847# endif
848# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]849 *IM_BRGC2 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]850# endif
851# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]852 *IM_BRGC3 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]853# endif
854# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]855 *IM_BRGC4 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]856# endif
857# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]858 *IM_BRGC5 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]859# endif
860# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]861 *IM_BRGC6 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]862# endif
863# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]864 *IM_BRGC7 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]865# endif
866# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]867 *IM_BRGC8 = temp_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]868# endif
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]869
870 /*
871 * Enable LRCLK BRG (2nd time - permanent)
872 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]873# if (LRCLK_BRG == 0)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]874 *IM_BRGC1 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]875# endif
876# if (LRCLK_BRG == 1)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]877 *IM_BRGC2 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]878# endif
879# if (LRCLK_BRG == 2)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]880 *IM_BRGC3 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]881# endif
882# if (LRCLK_BRG == 3)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]883 *IM_BRGC4 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]884# endif
885# if (LRCLK_BRG == 4)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]886 *IM_BRGC5 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]887# endif
888# if (LRCLK_BRG == 5)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]889 *IM_BRGC6 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]890# endif
891# if (LRCLK_BRG == 6)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]892 *IM_BRGC7 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]893# endif
894# if (LRCLK_BRG == 7)
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]895 *IM_BRGC8 = real_lrclk_brg;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]896# endif
wdenkc217f6d2002-11-11 02:11:37 +0000[diff] [blame]897
898 /*
899 * Restore the Interrupt state
900 */
901 if (flag) {
902 enable_interrupts();
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]903 }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]904# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]905 /*
906 * Enable the clocks
907 */
908 Daq_BRG_Enable(LRCLK_BRG);
909 Daq_BRG_Enable(SCLK_BRG);
910 Daq_BRG_Enable(MCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]911# endif
912}
913
914void Daq_Display_Clocks(void)
915
916{
917 volatile immap_t *immr = (immap_t *)CFG_IMMR;
918 uint mclk_divisor; /* Detected MCLK divisor */
919 uint sclk_divisor; /* Detected SCLK divisor */
920
921 printf("\nBRG:\n");
922 if (immr->im_brgc4 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]923 printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]924 immr->im_brgc4,
925 (uint)&(immr->im_brgc4),
926 Daq_BRG_Get_Count(3),
927 Daq_BRG_Get_ExtClk(3),
928 Daq_BRG_Get_ExtClk_Description(3));
929 }
930 if (immr->im_brgc8 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]931 printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]932 immr->im_brgc8,
933 (uint)&(immr->im_brgc8),
934 Daq_BRG_Get_Count(7),
935 Daq_BRG_Get_ExtClk(7),
936 Daq_BRG_Get_ExtClk_Description(7));
937 }
938 if (immr->im_brgc6 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]939 printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]940 immr->im_brgc6,
941 (uint)&(immr->im_brgc6),
942 Daq_BRG_Get_Count(5),
943 Daq_BRG_Get_ExtClk(5),
944 Daq_BRG_Get_ExtClk_Description(5));
945 }
946 if (immr->im_brgc1 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]947 printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]948 immr->im_brgc1,
949 (uint)&(immr->im_brgc1),
950 Daq_BRG_Get_Count(0),
951 Daq_BRG_Get_ExtClk(0),
952 Daq_BRG_Get_ExtClk_Description(0));
953 }
954 if (immr->im_brgc2 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]955 printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]956 immr->im_brgc2,
957 (uint)&(immr->im_brgc2),
958 Daq_BRG_Get_Count(1),
959 Daq_BRG_Get_ExtClk(1),
960 Daq_BRG_Get_ExtClk_Description(1));
961 }
962 if (immr->im_brgc3 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]963 printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]964 immr->im_brgc3,
965 (uint)&(immr->im_brgc3),
966 Daq_BRG_Get_Count(2),
967 Daq_BRG_Get_ExtClk(2),
968 Daq_BRG_Get_ExtClk_Description(2));
969 }
970 if (immr->im_brgc5 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]971 printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]972 immr->im_brgc5,
973 (uint)&(immr->im_brgc5),
974 Daq_BRG_Get_Count(4),
975 Daq_BRG_Get_ExtClk(4),
976 Daq_BRG_Get_ExtClk_Description(4));
977 }
978 if (immr->im_brgc7 != 0) {
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]979 printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]980 immr->im_brgc7,
981 (uint)&(immr->im_brgc7),
982 Daq_BRG_Get_Count(6),
983 Daq_BRG_Get_ExtClk(6),
984 Daq_BRG_Get_ExtClk_Description(6));
985 }
986
987# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]988 mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]989# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]990 mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]991# endif
992# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]993 sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]994# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]995 sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]996# endif
997
998 printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
999 printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
1000 Daq_BRG_Rate(MCLK_BRG),
1001 mclk_divisor,
1002 mclk_divisor * sclk_divisor);
1003# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]1004 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1005 Daq_BRG_Rate(SCLK_BRG),
1006 sclk_divisor);
1007# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]1008 printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1009 Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
1010 sclk_divisor);
1011# endif
1012# ifdef RUN_LRCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]1013 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1014 Daq_BRG_Rate(LRCLK_BRG));
1015# else
1016# ifdef RUN_SCLK_ON_BRG_INT
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]1017 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1018 Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
1019# else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame^]1020 printf("\tLRCLK %8d Hz\n",
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1021 Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
1022# endif
1023# endif
1024 printf("\n");
1025}