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git01.mediatek.com / filogic / uboot / c958bbfcdba73980a9dbe0cb608ce0b88f84562a / . / arch / sandbox / dts / sandbox.dts
blob: f1637c80f640d4871a5e05d4641218966ce65787 [file] [log] [blame]
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]5/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]6 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]7 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]8 model = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]9
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]10 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]11 i2c0 = &i2c_0;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]12 pci0 = &pci;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]13 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]14 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]15 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]16 };
17
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]18 memory {
19 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
20 };
21
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]22 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]23 reg = <0 0>;
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]24 u-boot,dm-pre-reloc;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]25 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]26 };
27
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]28 dsi_host: dsi_host {
29 compatible = "sandbox,dsi-host";
30 status = "okay";
31 };
32
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]33 ethrawbus {
34 compatible = "sandbox,eth-raw-bus";
35 skip-localhost = <0>;
36 };
37
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]38 eth@10002000 {
39 compatible = "sandbox,eth";
40 reg = <0x10002000 0x1000>;
41 fake-host-hwaddr = [00 00 66 44 22 00];
42 };
43
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]44 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]45 #address-cells = <1>;
46 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]47 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]48 compatible = "sandbox,i2c";
49 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]52 };
53
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]54 pci: pci-controller {
55 compatible = "sandbox,pci";
56 device_type = "pci";
57 #address-cells = <3>;
58 #size-cells = <2>;
59 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
60 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]61 };
62
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]63 spi: spi@0 {
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]64 u-boot,dm-pre-reloc;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]65 #address-cells = <1>;
66 #size-cells = <0>;
67 reg = <0 0>;
68 compatible = "sandbox,spi";
69 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]70 };
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]71};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]72
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]73#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]74#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]75#include "sandbox_pmic.dtsi"