blob: c10dd28f61af5502fc97035ff094bdf5d5784e4b [file] [log] [blame]
Giuseppe Pagano23442e02013-11-28 12:32:48 +01001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/imx-common/iomux-v3.h>
8#include <asm/arch/iomux.h>
9#include <asm/io.h>
Stefano Babic52d60322013-12-19 11:04:33 +010010#include <asm/arch/clock.h>
Tim Harveyc877bca2014-05-07 22:24:47 -070011#include <asm/arch/sys_proto.h>
Giuseppe Pagano23442e02013-11-28 12:32:48 +010012
13int setup_sata(void)
14{
15 struct iomuxc_base_regs *const iomuxc_regs
16 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
Tim Harveyc877bca2014-05-07 22:24:47 -070017 int ret;
18
19 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
20 return 1;
Giuseppe Pagano23442e02013-11-28 12:32:48 +010021
Tim Harveyc877bca2014-05-07 22:24:47 -070022 ret = enable_sata_clock();
Giuseppe Pagano23442e02013-11-28 12:32:48 +010023 if (ret)
24 return ret;
25
26 clrsetbits_le32(&iomuxc_regs->gpr[13],
27 IOMUXC_GPR13_SATA_MASK,
28 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
29 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
30 |IOMUXC_GPR13_SATA_SPEED_3G
31 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
32 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
33 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
34 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
35 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
36 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
37
38 return 0;
39}