blob: 1b4c5029afbaf2947692476cae7f3042582b6d0e [file] [log] [blame]
Giuseppe Pagano23442e02013-11-28 12:32:48 +01001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/imx-common/iomux-v3.h>
8#include <asm/arch/iomux.h>
9#include <asm/io.h>
10
11int setup_sata(void)
12{
13 struct iomuxc_base_regs *const iomuxc_regs
14 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
15
16 int ret = enable_sata_clock();
17 if (ret)
18 return ret;
19
20 clrsetbits_le32(&iomuxc_regs->gpr[13],
21 IOMUXC_GPR13_SATA_MASK,
22 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
23 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
24 |IOMUXC_GPR13_SATA_SPEED_3G
25 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
26 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
27 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
28 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
29 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
30 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
31
32 return 0;
33}