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git01.mediatek.com / filogic / uboot / c8477d6b26c47ea68d015be3c8e3f2da5f0d2850 / . / drivers / ddr / marvell / a38x / ddr3_topology_def.h
blob: eda2b13f9049a4c9068e396c007d69a1221e2b80 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]4 */
5
6#ifndef _DDR3_TOPOLOGY_DEF_H
7#define _DDR3_TOPOLOGY_DEF_H
8
9/* TOPOLOGY */
10
11enum hws_speed_bin {
12 SPEED_BIN_DDR_800D,
13 SPEED_BIN_DDR_800E,
14 SPEED_BIN_DDR_1066E,
15 SPEED_BIN_DDR_1066F,
16 SPEED_BIN_DDR_1066G,
17 SPEED_BIN_DDR_1333F,
18 SPEED_BIN_DDR_1333G,
19 SPEED_BIN_DDR_1333H,
20 SPEED_BIN_DDR_1333J,
21 SPEED_BIN_DDR_1600G,
22 SPEED_BIN_DDR_1600H,
23 SPEED_BIN_DDR_1600J,
24 SPEED_BIN_DDR_1600K,
25 SPEED_BIN_DDR_1866J,
26 SPEED_BIN_DDR_1866K,
27 SPEED_BIN_DDR_1866L,
28 SPEED_BIN_DDR_1866M,
29 SPEED_BIN_DDR_2133K,
30 SPEED_BIN_DDR_2133L,
31 SPEED_BIN_DDR_2133M,
32 SPEED_BIN_DDR_2133N,
33
34 SPEED_BIN_DDR_1333H_EXT,
35 SPEED_BIN_DDR_1600K_EXT,
36 SPEED_BIN_DDR_1866M_EXT
37};
38
39enum hws_ddr_freq {
40 DDR_FREQ_LOW_FREQ,
41 DDR_FREQ_400,
42 DDR_FREQ_533,
43 DDR_FREQ_667,
44 DDR_FREQ_800,
45 DDR_FREQ_933,
46 DDR_FREQ_1066,
47 DDR_FREQ_311,
48 DDR_FREQ_333,
49 DDR_FREQ_467,
50 DDR_FREQ_850,
51 DDR_FREQ_600,
52 DDR_FREQ_300,
53 DDR_FREQ_900,
54 DDR_FREQ_360,
55 DDR_FREQ_1000,
56 DDR_FREQ_LIMIT
57};
58
59enum speed_bin_table_elements {
60 SPEED_BIN_TRCD,
61 SPEED_BIN_TRP,
62 SPEED_BIN_TRAS,
63 SPEED_BIN_TRC,
64 SPEED_BIN_TRRD1K,
65 SPEED_BIN_TRRD2K,
66 SPEED_BIN_TPD,
67 SPEED_BIN_TFAW1K,
68 SPEED_BIN_TFAW2K,
69 SPEED_BIN_TWTR,
70 SPEED_BIN_TRTP,
71 SPEED_BIN_TWR,
Chris Packham5450f0c2018-01-18 17:16:10 +1300[diff] [blame]72 SPEED_BIN_TMOD,
73 SPEED_BIN_TXPDLL
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]74};
75
76#endif /* _DDR3_TOPOLOGY_DEF_H */