ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
index 64a0447..a17eca0 100644
--- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
@@ -70,7 +70,8 @@
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
- SPEED_BIN_TMOD
+ SPEED_BIN_TMOD,
+ SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */