Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Functions related to OMAP3 SDRC. |
| 4 | * |
| 5 | * This file has been created after exctracting and consolidating |
| 6 | * the SDRC related content from mem.c and board.c, also created |
Maxim Uvarov | 74dde14 | 2023-12-26 21:46:18 +0600 | [diff] [blame] | 7 | * generic init function (omap3_mem_init). |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 8 | * |
| 9 | * Copyright (C) 2004-2010 |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 10 | * Texas Instruments Incorporated - https://www.ti.com/ |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 11 | * |
Simon Schwarz | ee50ca9 | 2011-09-14 15:15:37 -0400 | [diff] [blame] | 12 | * Copyright (C) 2011 |
| 13 | * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> |
| 14 | * |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 15 | * Author : |
| 16 | * Vaibhav Hiremath <hvaibhav@ti.com> |
| 17 | * |
| 18 | * Original implementation by (mem.c, board.c) : |
| 19 | * Sunil Kumar <sunilsaini05@gmail.com> |
| 20 | * Shashi Ranjan <shashiranjanmca05@gmail.com> |
| 21 | * Manikandan Pillai <mani.pillai@ti.com> |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 22 | */ |
| 23 | |
| 24 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 25 | #include <init.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 26 | #include <asm/global_data.h> |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 27 | #include <asm/io.h> |
| 28 | #include <asm/arch/mem.h> |
| 29 | #include <asm/arch/sys_proto.h> |
| 30 | |
Nishanth Menon | edded0e4 | 2010-12-11 11:41:42 -0500 | [diff] [blame] | 31 | DECLARE_GLOBAL_DATA_PTR; |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 32 | extern omap3_sysinfo sysinfo; |
| 33 | |
| 34 | static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; |
| 35 | |
| 36 | /* |
| 37 | * is_mem_sdr - |
| 38 | * - Return 1 if mem type in use is SDR |
| 39 | */ |
| 40 | u32 is_mem_sdr(void) |
| 41 | { |
| 42 | if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) |
| 43 | return 1; |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | /* |
Adam Ford | 3a8059e | 2022-02-12 06:12:41 -0600 | [diff] [blame] | 48 | * get_sdr_cs_size - |
| 49 | * - Get size of chip select 0/1 |
| 50 | */ |
| 51 | static u32 get_sdr_cs_size(u32 cs) |
| 52 | { |
| 53 | u32 size; |
| 54 | |
| 55 | /* get ram size field */ |
| 56 | size = readl(&sdrc_base->cs[cs].mcfg) >> 8; |
| 57 | size &= 0x3FF; /* remove unwanted bits */ |
| 58 | size <<= 21; /* multiply by 2 MiB to find size in MB */ |
| 59 | return size; |
| 60 | } |
| 61 | |
| 62 | /* |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 63 | * make_cs1_contiguous - |
Tom Rini | 858df78 | 2011-11-18 12:47:59 +0000 | [diff] [blame] | 64 | * - When we have CS1 populated we want to have it mapped after cs0 to allow |
| 65 | * command line mem=xyz use all memory with out discontinuous support |
| 66 | * compiled in. We could do it in the ATAG, but there really is two banks... |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 67 | */ |
Adam Ford | 3a8059e | 2022-02-12 06:12:41 -0600 | [diff] [blame] | 68 | static void make_cs1_contiguous(void) |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 69 | { |
| 70 | u32 size, a_add_low, a_add_high; |
| 71 | |
| 72 | size = get_sdr_cs_size(CS0); |
| 73 | size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ |
| 74 | a_add_high = (size & 3) << 8; /* set up low field */ |
| 75 | a_add_low = (size & 0x3C) >> 2; /* set up high field */ |
| 76 | writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); |
| 77 | |
| 78 | } |
| 79 | |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 80 | /* |
| 81 | * get_sdr_cs_offset - |
| 82 | * - Get offset of cs from cs0 start |
| 83 | */ |
| 84 | u32 get_sdr_cs_offset(u32 cs) |
| 85 | { |
| 86 | u32 offset; |
| 87 | |
| 88 | if (!cs) |
| 89 | return 0; |
| 90 | |
| 91 | offset = readl(&sdrc_base->cs_cfg); |
Tom Rini | d639cf5 | 2012-01-18 08:28:50 +0000 | [diff] [blame] | 92 | offset = (offset & 15) << 27 | (offset & 0x300) << 17; |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 93 | |
| 94 | return offset; |
| 95 | } |
| 96 | |
| 97 | /* |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 98 | * write_sdrc_timings - |
| 99 | * - Takes CS and associated timings and initalize SDRAM |
| 100 | * - Test CS to make sure it's OK for use |
| 101 | */ |
| 102 | static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 103 | struct board_sdrc_timings *timings) |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 104 | { |
| 105 | /* Setup timings we got from the board. */ |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 106 | writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); |
| 107 | writel(timings->ctrla, &sdrc_actim_base->ctrla); |
| 108 | writel(timings->ctrlb, &sdrc_actim_base->ctrlb); |
| 109 | writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 110 | writel(CMD_NOP, &sdrc_base->cs[cs].manual); |
| 111 | writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); |
| 112 | writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); |
| 113 | writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 114 | writel(timings->mr, &sdrc_base->cs[cs].mr); |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Test ram in this bank |
| 118 | * Disable if bad or not present |
| 119 | */ |
| 120 | if (!mem_ok(cs)) |
| 121 | writel(0, &sdrc_base->cs[cs].mcfg); |
| 122 | } |
| 123 | |
| 124 | /* |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 125 | * do_sdrc_init - |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 126 | * - Code called once in C-Stack only context for CS0 and with early being |
| 127 | * true and a possible 2nd time depending on memory configuration from |
| 128 | * stack+global context. |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 129 | */ |
Adam Ford | 3a8059e | 2022-02-12 06:12:41 -0600 | [diff] [blame] | 130 | static void do_sdrc_init(u32 cs, u32 early) |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 131 | { |
Steve Sakoman | a7561cc | 2010-08-19 20:09:57 -0700 | [diff] [blame] | 132 | struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 133 | struct board_sdrc_timings timings; |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 134 | |
| 135 | sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; |
| 136 | sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 137 | |
Albert ARIBAUD \(3ADEV\) | 70988eb | 2015-01-16 09:09:48 +0100 | [diff] [blame] | 138 | /* set some default timings */ |
| 139 | timings.sharing = SDRC_SHARING; |
| 140 | |
Tom Rini | 05800b9 | 2011-11-18 12:48:06 +0000 | [diff] [blame] | 141 | /* |
| 142 | * When called in the early context this may be SPL and we will |
| 143 | * need to set all of the timings. This ends up being board |
| 144 | * specific so we call a helper function to take care of this |
| 145 | * for us. Otherwise, to be safe, we need to copy the settings |
| 146 | * from the first bank to the second. We will setup CS0, |
| 147 | * then set cs_cfg to the appropriate value then try and |
| 148 | * setup CS1. |
| 149 | */ |
| 150 | #ifdef CONFIG_SPL_BUILD |
Albert ARIBAUD \(3ADEV\) | 70988eb | 2015-01-16 09:09:48 +0100 | [diff] [blame] | 151 | /* set/modify board-specific timings */ |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 152 | get_board_mem_timings(&timings); |
Tom Rini | 05800b9 | 2011-11-18 12:48:06 +0000 | [diff] [blame] | 153 | #endif |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 154 | if (early) { |
| 155 | /* reset sdrc controller */ |
| 156 | writel(SOFTRESET, &sdrc_base->sysconfig); |
| 157 | wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, |
| 158 | 12000000); |
| 159 | writel(0, &sdrc_base->sysconfig); |
| 160 | |
| 161 | /* setup sdrc to ball mux */ |
Albert ARIBAUD \(3ADEV\) | 70988eb | 2015-01-16 09:09:48 +0100 | [diff] [blame] | 162 | writel(timings.sharing, &sdrc_base->sharing); |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 163 | |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 164 | /* Disable Power Down of CKE because of 1 CKE on combo part */ |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 165 | writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, |
| 166 | &sdrc_base->power); |
| 167 | |
| 168 | writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); |
| 169 | sdelay(0x20000); |
Simon Schwarz | ee50ca9 | 2011-09-14 15:15:37 -0400 | [diff] [blame] | 170 | #ifdef CONFIG_SPL_BUILD |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 171 | write_sdrc_timings(CS0, sdrc_actim_base0, &timings); |
Tom Rini | 05800b9 | 2011-11-18 12:48:06 +0000 | [diff] [blame] | 172 | make_cs1_contiguous(); |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 173 | write_sdrc_timings(CS1, sdrc_actim_base1, &timings); |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 174 | #endif |
Simon Schwarz | ee50ca9 | 2011-09-14 15:15:37 -0400 | [diff] [blame] | 175 | |
Simon Schwarz | ee50ca9 | 2011-09-14 15:15:37 -0400 | [diff] [blame] | 176 | } |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 177 | |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 178 | /* |
Tom Rini | 4633d8e | 2011-11-18 12:48:00 +0000 | [diff] [blame] | 179 | * If we aren't using SPL we have been loaded by some |
| 180 | * other means which may not have correctly initialized |
| 181 | * both CS0 and CS1 (such as some older versions of x-loader) |
| 182 | * so we may be asked now to setup CS1. |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 183 | */ |
Simon Schwarz | ee50ca9 | 2011-09-14 15:15:37 -0400 | [diff] [blame] | 184 | if (cs == CS1) { |
Peter Barada | edb5c2f | 2012-11-13 07:40:28 +0000 | [diff] [blame] | 185 | timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), |
| 186 | timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); |
| 187 | timings.ctrla = readl(&sdrc_actim_base0->ctrla); |
| 188 | timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); |
| 189 | timings.mr = readl(&sdrc_base->cs[CS0].mr); |
| 190 | write_sdrc_timings(cs, sdrc_actim_base1, &timings); |
Steve Sakoman | a7561cc | 2010-08-19 20:09:57 -0700 | [diff] [blame] | 191 | } |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | /* |
| 195 | * dram_init - |
| 196 | * - Sets uboots idea of sdram size |
| 197 | */ |
| 198 | int dram_init(void) |
| 199 | { |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 200 | unsigned int size0 = 0, size1 = 0; |
| 201 | |
| 202 | size0 = get_sdr_cs_size(CS0); |
| 203 | /* |
Tom Rini | 858df78 | 2011-11-18 12:47:59 +0000 | [diff] [blame] | 204 | * We always need to have cs_cfg point at where the second |
| 205 | * bank would be, if present. Failure to do so can lead to |
| 206 | * strange situations where memory isn't detected and |
| 207 | * configured correctly. CS0 will already have been setup |
| 208 | * at this point. |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 209 | */ |
Tom Rini | 858df78 | 2011-11-18 12:47:59 +0000 | [diff] [blame] | 210 | make_cs1_contiguous(); |
| 211 | do_sdrc_init(CS1, NOT_EARLY); |
| 212 | size1 = get_sdr_cs_size(CS1); |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 213 | |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 214 | gd->ram_size = size0 + size1; |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 219 | int dram_init_banksize(void) |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 220 | { |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 221 | unsigned int size0 = 0, size1 = 0; |
| 222 | |
| 223 | size0 = get_sdr_cs_size(CS0); |
| 224 | size1 = get_sdr_cs_size(CS1); |
| 225 | |
| 226 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 227 | gd->bd->bi_dram[0].size = size0; |
| 228 | gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); |
| 229 | gd->bd->bi_dram[1].size = size1; |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 230 | |
| 231 | return 0; |
Heiko Schocher | 56d0a4d | 2010-09-17 13:10:41 +0200 | [diff] [blame] | 232 | } |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 233 | |
| 234 | /* |
Maxim Uvarov | 74dde14 | 2023-12-26 21:46:18 +0600 | [diff] [blame] | 235 | * omap3_mem_init - |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 236 | * - Init the sdrc chip, |
| 237 | * - Selects CS0 and CS1, |
| 238 | */ |
Maxim Uvarov | 74dde14 | 2023-12-26 21:46:18 +0600 | [diff] [blame] | 239 | void omap3_mem_init(void) |
Vaibhav Hiremath | 558d23d | 2010-06-07 15:20:34 -0400 | [diff] [blame] | 240 | { |
| 241 | /* only init up first bank here */ |
| 242 | do_sdrc_init(CS0, EARLY_INIT); |
| 243 | } |