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developer7305b4c2020-04-21 09:28:49 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7628_H
9#define __CONFIG_MT7628_H
10
developer7305b4c2020-04-21 09:28:49 +020011#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
12
developer7305b4c2020-04-21 09:28:49 +020013#define CONFIG_SYS_SDRAM_BASE 0x80000000
developer7305b4c2020-04-21 09:28:49 +020014
15#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
16
17#define CONFIG_SYS_BOOTM_LEN 0x1000000
18
developer7305b4c2020-04-21 09:28:49 +020019/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -060020#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
developer7305b4c2020-04-21 09:28:49 +020021#define CONFIG_SYS_NS16550_MEM32
22#define CONFIG_SYS_NS16550_CLK 40000000
23#define CONFIG_SYS_NS16550_REG_SIZE -4
24#define CONFIG_SYS_NS16550_COM1 0xb0000c00
developer7305b4c2020-04-21 09:28:49 +020025#endif
26
27/* Serial common */
28#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
29 230400, 460800, 921600 }
30
31/* SPL */
developer7305b4c2020-04-21 09:28:49 +020032
33#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
developer7305b4c2020-04-21 09:28:49 +020034
35/* Dummy value */
36#define CONFIG_SYS_UBOOT_BASE 0
37
38#endif /* __CONFIG_MT7628_H */