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Wang Huan8ce6bec2014-09-05 13:52:34 +08001/*
2 * Copyright 2014, Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARMV7_LS102XA_CONFIG_
8#define _ASM_ARMV7_LS102XA_CONFIG_
9
Wang Huan8ce6bec2014-09-05 13:52:34 +080010#define OCRAM_BASE_ADDR 0x10000000
Hongbo Zhang912b3812016-07-21 18:09:39 +080011#define OCRAM_SIZE 0x00010000
Xiubo Li563e3ce2014-11-21 17:40:57 +080012#define OCRAM_BASE_S_ADDR 0x10010000
13#define OCRAM_S_SIZE 0x00010000
Wang Huan8ce6bec2014-09-05 13:52:34 +080014
15#define CONFIG_SYS_IMMR 0x01000000
chenhui zhao0c789872014-10-22 18:20:22 +080016#define CONFIG_SYS_DCSRBAR 0x20000000
Wang Huan8ce6bec2014-09-05 13:52:34 +080017
Alison Wangab98bb52014-12-09 17:38:14 +080018#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
York Sun48d55ac2016-09-26 08:09:30 -070019#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
Alison Wangab98bb52014-12-09 17:38:14 +080020
York Sun48d55ac2016-09-26 08:09:30 -070021#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
Wang Huan8ce6bec2014-09-05 13:52:34 +080022#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
23#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
Xiubo Li54de0652014-11-21 17:40:58 +080024#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
Wang Huan8ce6bec2014-09-05 13:52:34 +080025#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
26#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
27#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
Ruchika Gupta901ae762014-10-15 11:39:06 +053028#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
29#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
gaurav rana8b5ea652015-02-27 09:46:17 +053030#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
31#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
Wang Huan8ce6bec2014-09-05 13:52:34 +080032#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
33#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
34#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
Hongbo Zhang4f6e6102016-07-21 18:09:38 +080035#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
Wang Huan8ce6bec2014-09-05 13:52:34 +080036#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
37#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
Wang Huan4779d4a2014-09-05 13:52:48 +080038#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
Rajesh Bhagat386f2e42016-06-07 18:59:34 +053039#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
40#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
Wang Huan8ce6bec2014-09-05 13:52:34 +080041
Alison Wanga825bb32015-01-16 17:21:34 +080042#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
Alex Porosanu177fca82016-04-29 15:17:58 +030043#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
Wang Huan8ce6bec2014-09-05 13:52:34 +080044#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
45#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
46#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
47#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
48
49#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
50#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
51
52#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
53
54#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
55#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
56#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
57
58#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
59
60#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
61#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
62
63#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
64
Minghuan Liana4d6b612014-10-31 13:43:44 +080065#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
66#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
67
Minghuan Lian6c9afed2015-01-21 17:29:17 +080068#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
69#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
70#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
71#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
72#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
73/*
74 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
75 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
76 */
77#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
78 CONFIG_SYS_PCIE1_VIRT_ADDR)
79#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
80 CONFIG_SYS_PCIE2_VIRT_ADDR)
81
tang yuantian9f51db22015-10-16 16:06:05 +080082/* SATA */
83#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
Simon Glass8706b812016-05-01 11:36:02 -060084#define CONFIG_SCSI
tang yuantian9f51db22015-10-16 16:06:05 +080085#define CONFIG_LIBATA
86#define CONFIG_SCSI_AHCI
87#define CONFIG_SCSI_AHCI_PLAT
88#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
89#define CONFIG_SYS_SCSI_MAX_LUN 1
90#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
91 CONFIG_SYS_SCSI_MAX_LUN)
Wang Huan8ce6bec2014-09-05 13:52:34 +080092#ifdef CONFIG_DDR_SPD
Wang Huan8ce6bec2014-09-05 13:52:34 +080093#define CONFIG_VERY_BIG_RAM
Wang Huan8ce6bec2014-09-05 13:52:34 +080094#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
95#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
96#endif
97
98#define CONFIG_SYS_FSL_IFC_BE
99#define CONFIG_SYS_FSL_ESDHC_BE
100#define CONFIG_SYS_FSL_WDOG_BE
101#define CONFIG_SYS_FSL_DSPI_BE
102#define CONFIG_SYS_FSL_QSPI_BE
Wang Huan4779d4a2014-09-05 13:52:48 +0800103#define CONFIG_SYS_FSL_DCU_BE
gaurav rana8b5ea652015-02-27 09:46:17 +0530104#define CONFIG_SYS_FSL_SEC_MON_LE
gaurav rana8b5ea652015-02-27 09:46:17 +0530105#define CONFIG_SYS_FSL_SFP_VER_3_2
106#define CONFIG_SYS_FSL_SFP_BE
107#define CONFIG_SYS_FSL_SRK_LE
Wang Huan4779d4a2014-09-05 13:52:48 +0800108
109#define DCU_LAYER_MAX_NUM 16
Wang Huan8ce6bec2014-09-05 13:52:34 +0800110
York Sunc4f047c2017-03-27 11:41:03 -0700111#ifdef CONFIG_ARCH_LS1021A
Nikhil Badolad3d6e702014-10-17 11:35:46 +0530112#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Alex Porosanub4848d02016-04-29 15:17:59 +0300113#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
Wang Huan8ce6bec2014-09-05 13:52:34 +0800114#else
115#error SoC not defined
116#endif
117
Alison Wang92fc30d2014-12-26 13:14:01 +0800118#define FSL_IFC_COMPAT "fsl,ifc"
Alison Wang88a931f2016-02-29 14:50:20 +0800119#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
120#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
Alison Wang92fc30d2014-12-26 13:14:01 +0800121
Wang Huan8ce6bec2014-09-05 13:52:34 +0800122#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */