blob: 909e566acf5e1e193db39bdfb1e43aa680efeeec [file] [log] [blame]
Ramon Friede43d8e72018-05-16 12:13:40 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TLMM driver for Qualcomm APQ8016, APQ8096
4 *
5 * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
6 *
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <asm/io.h>
Sumit Gargb7572e52022-07-27 13:52:04 +053013#include <dm/device_compat.h>
Caleb Connolly506eb532023-11-14 12:55:40 +000014#include <dm/device-internal.h>
Sumit Gargb7572e52022-07-27 13:52:04 +053015#include <dm/lists.h>
Caleb Connollyfabb8972023-11-14 12:55:42 +000016#include <asm/gpio.h>
Ramon Friede43d8e72018-05-16 12:13:40 +030017#include <dm/pinctrl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Caleb Connolly190005c2024-02-26 17:26:17 +000019#include <linux/bug.h>
Caleb Connollyfabb8972023-11-14 12:55:42 +000020#include <mach/gpio.h>
21
Caleb Connolly506eb532023-11-14 12:55:40 +000022#include "pinctrl-qcom.h"
Ramon Friede43d8e72018-05-16 12:13:40 +030023
24struct msm_pinctrl_priv {
25 phys_addr_t base;
26 struct msm_pinctrl_data *data;
27};
28
Caleb Connollyfabb8972023-11-14 12:55:42 +000029#define GPIO_CONFIG_REG(priv, x) \
30 (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
31
Ramon Friede43d8e72018-05-16 12:13:40 +030032#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
33#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
34#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
Ramon Fried772a99a2019-01-12 11:47:27 +020035#define TLMM_GPIO_DISABLE BIT(9)
Ramon Friede43d8e72018-05-16 12:13:40 +030036
37static const struct pinconf_param msm_conf_params[] = {
Sumit Gargfd1ad932023-02-01 19:28:52 +053038 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
Ramon Friede43d8e72018-05-16 12:13:40 +030039 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
Sumit Gargfd1ad932023-02-01 19:28:52 +053040 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
Ramon Friede43d8e72018-05-16 12:13:40 +030041};
42
43static int msm_get_functions_count(struct udevice *dev)
44{
45 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
46
47 return priv->data->functions_count;
48}
49
50static int msm_get_pins_count(struct udevice *dev)
51{
52 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
53
Caleb Connollyfabb8972023-11-14 12:55:42 +000054 return priv->data->pin_data.pin_count;
Ramon Friede43d8e72018-05-16 12:13:40 +030055}
56
57static const char *msm_get_function_name(struct udevice *dev,
58 unsigned int selector)
59{
60 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
61
62 return priv->data->get_function_name(dev, selector);
63}
64
65static int msm_pinctrl_probe(struct udevice *dev)
66{
67 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
68
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +090069 priv->base = dev_read_addr(dev);
Caleb Connollyfabb8972023-11-14 12:55:42 +000070 priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
Ramon Friede43d8e72018-05-16 12:13:40 +030071
72 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
73}
74
75static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
76{
77 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
78
79 return priv->data->get_pin_name(dev, selector);
80}
81
82static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
83 unsigned int func_selector)
84{
85 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
Volodymyr Babchukc4cc9792024-03-11 21:33:46 +000086 u32 func = priv->data->get_function_mux(pin_selector, func_selector);
Ramon Friede43d8e72018-05-16 12:13:40 +030087
Caleb Connolly190005c2024-02-26 17:26:17 +000088 /* Always NOP for special pins, assume they're in the correct state */
89 if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
90 return 0;
91
Caleb Connollyfabb8972023-11-14 12:55:42 +000092 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
Volodymyr Babchukc4cc9792024-03-11 21:33:46 +000093 TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
Ramon Friede43d8e72018-05-16 12:13:40 +030094 return 0;
95}
96
97static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
98 unsigned int param, unsigned int argument)
99{
100 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
101
Caleb Connolly190005c2024-02-26 17:26:17 +0000102 /* Always NOP for special pins */
103 if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
104 return 0;
105
Ramon Friede43d8e72018-05-16 12:13:40 +0300106 switch (param) {
107 case PIN_CONFIG_DRIVE_STRENGTH:
Sumit Gargfd1ad932023-02-01 19:28:52 +0530108 argument = (argument / 2) - 1;
Caleb Connollyfabb8972023-11-14 12:55:42 +0000109 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
Ramon Friede43d8e72018-05-16 12:13:40 +0300110 TLMM_DRV_STRENGTH_MASK, argument << 6);
111 break;
112 case PIN_CONFIG_BIAS_DISABLE:
Caleb Connollyfabb8972023-11-14 12:55:42 +0000113 clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
Ramon Friede43d8e72018-05-16 12:13:40 +0300114 TLMM_GPIO_PULL_MASK);
115 break;
Sumit Gargfd1ad932023-02-01 19:28:52 +0530116 case PIN_CONFIG_BIAS_PULL_UP:
Caleb Connollyfabb8972023-11-14 12:55:42 +0000117 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
Sumit Gargfd1ad932023-02-01 19:28:52 +0530118 TLMM_GPIO_PULL_MASK, argument);
119 break;
Ramon Friede43d8e72018-05-16 12:13:40 +0300120 default:
121 return 0;
122 }
123
124 return 0;
125}
126
Caleb Connolly506eb532023-11-14 12:55:40 +0000127struct pinctrl_ops msm_pinctrl_ops = {
Ramon Friede43d8e72018-05-16 12:13:40 +0300128 .get_pins_count = msm_get_pins_count,
129 .get_pin_name = msm_get_pin_name,
130 .set_state = pinctrl_generic_set_state,
131 .pinmux_set = msm_pinmux_set,
132 .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
133 .pinconf_params = msm_conf_params,
134 .pinconf_set = msm_pinconf_set,
135 .get_functions_count = msm_get_functions_count,
136 .get_function_name = msm_get_function_name,
137};
138
Caleb Connolly506eb532023-11-14 12:55:40 +0000139int msm_pinctrl_bind(struct udevice *dev)
Sumit Gargb7572e52022-07-27 13:52:04 +0530140{
141 ofnode node = dev_ofnode(dev);
Caleb Connolly506eb532023-11-14 12:55:40 +0000142 struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
143 struct driver *drv;
144 struct udevice *pinctrl_dev;
Sumit Gargb7572e52022-07-27 13:52:04 +0530145 const char *name;
146 int ret;
147
Caleb Connolly190005c2024-02-26 17:26:17 +0000148 if (!data->pin_data.special_pins_start)
149 dev_warn(dev, "Special pins start index not defined!\n");
150
Caleb Connolly506eb532023-11-14 12:55:40 +0000151 drv = lists_driver_lookup_name("pinctrl_qcom");
152 if (!drv)
153 return -ENOENT;
154
155 ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data,
156 dev_ofnode(dev), &pinctrl_dev);
157 if (ret)
158 return ret;
159
Sumit Gargb7572e52022-07-27 13:52:04 +0530160 ofnode_get_property(node, "gpio-controller", &ret);
161 if (ret < 0)
162 return 0;
163
164 /* Get the name of gpio node */
165 name = ofnode_get_name(node);
166 if (!name)
167 return -EINVAL;
168
Caleb Connollyfabb8972023-11-14 12:55:42 +0000169 drv = lists_driver_lookup_name("gpio_msm");
170 if (!drv) {
171 printf("Can't find gpio_msm driver\n");
172 return -ENODEV;
173 }
174
175 /* Bind gpio device as a child of the pinctrl device */
176 ret = device_bind_with_driver_data(pinctrl_dev, drv,
177 name, (ulong)&data->pin_data, node, NULL);
Caleb Connolly506eb532023-11-14 12:55:40 +0000178 if (ret) {
179 device_unbind(pinctrl_dev);
Sumit Gargb7572e52022-07-27 13:52:04 +0530180 return ret;
Caleb Connolly506eb532023-11-14 12:55:40 +0000181 }
Sumit Gargb7572e52022-07-27 13:52:04 +0530182
183 return 0;
184}
185
Caleb Connolly506eb532023-11-14 12:55:40 +0000186U_BOOT_DRIVER(pinctrl_qcom) = {
187 .name = "pinctrl_qcom",
Ramon Friede43d8e72018-05-16 12:13:40 +0300188 .id = UCLASS_PINCTRL,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700189 .priv_auto = sizeof(struct msm_pinctrl_priv),
Ramon Friede43d8e72018-05-16 12:13:40 +0300190 .ops = &msm_pinctrl_ops,
191 .probe = msm_pinctrl_probe,
Ramon Friede43d8e72018-05-16 12:13:40 +0300192};