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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
Finley Xiao20d52a02019-09-25 17:57:49 +020095config ROCKCHIP_OTP
96 bool "Rockchip OTP Support"
97 depends on MISC
98 help
99 Enable (read-only) access for the one-time-programmable memory block
100 found in Rockchip SoCs: accesses can either be made using byte
101 addressing and a length or through child-nodes that are generated
102 based on the e-fuse map retrieved from the DTS.
103
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530104config SIFIVE_OTP
105 bool "SiFive eMemory OTP driver"
106 depends on MISC
107 help
108 Enable support for reading and writing the eMemory OTP on the
109 SiFive SoCs.
110
Tom Rini035e8722022-11-19 18:45:33 -0500111config SMSC_LPC47M
112 bool "LPC47M SMSC driver"
113
114config SMSC_SIO1007
115 bool "SIO1007 SMSC driver"
116
Liviu Dudau688db7f2018-09-28 13:43:31 +0100117config VEXPRESS_CONFIG
118 bool "Enable support for Arm Versatile Express config bus"
119 depends on MISC
120 help
121 If you say Y here, you will get support for accessing the
122 configuration bus on the Arm Versatile Express boards via
123 a sysreg driver.
124
Simon Glass036ca142023-09-10 13:13:02 -0600125config CBMEM_CONSOLE
126 bool "Write console output to coreboot cbmem"
127 depends on X86
128 help
129 Enables console output to the cbmem console, which is a memory
130 region set up by coreboot to hold a record of all console output.
131 Enable this only if booting from coreboot.
132
Simon Glass5b79bb22015-02-13 12:20:47 -0700133config CMD_CROS_EC
134 bool "Enable crosec command"
135 depends on CROS_EC
136 help
137 Enable command-line access to the Chrome OS EC (Embedded
138 Controller). This provides the 'crosec' command which has
139 a number of sub-commands for performing EC tasks such as
140 updating its flash, accessing a small saved context area
141 and talking to the I2C bus behind the EC (if there is one).
142
143config CROS_EC
144 bool "Enable Chrome OS EC"
145 help
146 Enable access to the Chrome OS EC. This is a separate
147 microcontroller typically available on a SPI bus on Chromebooks. It
148 provides access to the keyboard, some internal storage and may
149 control access to the battery and main PMIC depending on the
150 device. You can use the 'crosec' command to access it.
151
Simon Glass605931c2018-11-18 08:14:27 -0700152config SPL_CROS_EC
153 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400154 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700155 help
156 Enable access to the Chrome OS EC in SPL. This is a separate
157 microcontroller typically available on a SPI bus on Chromebooks. It
158 provides access to the keyboard, some internal storage and may
159 control access to the battery and main PMIC depending on the
160 device. You can use the 'crosec' command to access it.
161
162config TPL_CROS_EC
163 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400164 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700165 help
166 Enable access to the Chrome OS EC in TPL. This is a separate
167 microcontroller typically available on a SPI bus on Chromebooks. It
168 provides access to the keyboard, some internal storage and may
169 control access to the battery and main PMIC depending on the
170 device. You can use the 'crosec' command to access it.
171
Simon Glasse7ca7da2022-04-30 00:56:53 -0600172config VPL_CROS_EC
173 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400174 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600175 help
176 Enable access to the Chrome OS EC in VPL. This is a separate
177 microcontroller typically available on a SPI bus on Chromebooks. It
178 provides access to the keyboard, some internal storage and may
179 control access to the battery and main PMIC depending on the
180 device. You can use the 'crosec' command to access it.
181
Simon Glass5b79bb22015-02-13 12:20:47 -0700182config CROS_EC_I2C
183 bool "Enable Chrome OS EC I2C driver"
184 depends on CROS_EC
185 help
186 Enable I2C access to the Chrome OS EC. This is used on older
187 ARM Chromebooks such as snow and spring before the standard bus
188 changed to SPI. The EC will accept commands across the I2C using
189 a special message protocol, and provide responses.
190
191config CROS_EC_LPC
192 bool "Enable Chrome OS EC LPC driver"
193 depends on CROS_EC
194 help
195 Enable I2C access to the Chrome OS EC. This is used on x86
196 Chromebooks such as link and falco. The keyboard is provided
197 through a legacy port interface, so on x86 machines the main
198 function of the EC is power and thermal management.
199
Simon Glass605931c2018-11-18 08:14:27 -0700200config SPL_CROS_EC_LPC
201 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400202 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700203 help
204 Enable I2C access to the Chrome OS EC. This is used on x86
205 Chromebooks such as link and falco. The keyboard is provided
206 through a legacy port interface, so on x86 machines the main
207 function of the EC is power and thermal management.
208
209config TPL_CROS_EC_LPC
210 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400211 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700212 help
213 Enable I2C access to the Chrome OS EC. This is used on x86
214 Chromebooks such as link and falco. The keyboard is provided
215 through a legacy port interface, so on x86 machines the main
216 function of the EC is power and thermal management.
217
Simon Glasse7ca7da2022-04-30 00:56:53 -0600218config VPL_CROS_EC_LPC
219 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400220 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600221 help
222 Enable I2C access to the Chrome OS EC. This is used on x86
223 Chromebooks such as link and falco. The keyboard is provided
224 through a legacy port interface, so on x86 machines the main
225 function of the EC is power and thermal management.
226
Simon Glassc6e06692015-03-26 09:29:40 -0600227config CROS_EC_SANDBOX
228 bool "Enable Chrome OS EC sandbox driver"
229 depends on CROS_EC && SANDBOX
230 help
231 Enable a sandbox emulation of the Chrome OS EC. This supports
232 keyboard (use the -l flag to enable the LCD), verified boot context,
233 EC flash read/write/erase support and a few other things. It is
234 enough to perform a Chrome OS verified boot on sandbox.
235
Simon Glass605931c2018-11-18 08:14:27 -0700236config SPL_CROS_EC_SANDBOX
237 bool "Enable Chrome OS EC sandbox driver in SPL"
238 depends on SPL_CROS_EC && SANDBOX
239 help
240 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
241 keyboard (use the -l flag to enable the LCD), verified boot context,
242 EC flash read/write/erase support and a few other things. It is
243 enough to perform a Chrome OS verified boot on sandbox.
244
245config TPL_CROS_EC_SANDBOX
246 bool "Enable Chrome OS EC sandbox driver in TPL"
247 depends on TPL_CROS_EC && SANDBOX
248 help
249 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
250 keyboard (use the -l flag to enable the LCD), verified boot context,
251 EC flash read/write/erase support and a few other things. It is
252 enough to perform a Chrome OS verified boot on sandbox.
253
Simon Glasse7ca7da2022-04-30 00:56:53 -0600254config VPL_CROS_EC_SANDBOX
255 bool "Enable Chrome OS EC sandbox driver in VPL"
256 depends on VPL_CROS_EC && SANDBOX
257 help
258 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
259 keyboard (use the -l flag to enable the LCD), verified boot context,
260 EC flash read/write/erase support and a few other things. It is
261 enough to perform a Chrome OS verified boot on sandbox.
262
Simon Glass5b79bb22015-02-13 12:20:47 -0700263config CROS_EC_SPI
264 bool "Enable Chrome OS EC SPI driver"
265 depends on CROS_EC
266 help
267 Enable SPI access to the Chrome OS EC. This is used on newer
268 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
269 provides a faster and more robust interface than I2C but the bugs
270 are less interesting.
271
Simon Glass58ed3222017-05-17 03:25:02 -0600272config DS4510
273 bool "Enable support for DS4510 CPU supervisor"
274 help
275 Enable support for the Maxim DS4510 CPU supervisor. It has an
276 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
277 and a configurable timer for the supervisor function. The device is
278 connected over I2C.
279
Tom Rini66fa77a2022-11-19 18:45:11 -0500280config FSL_IIM
281 bool "Enable FSL IC Identification Module (IIM) driver"
282 depends on ARCH_MX31 || ARCH_MX5
283
Peng Fanfb6166a2015-08-26 15:41:33 +0800284config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530285 bool "Enable FSL SEC_MON Driver"
286 help
287 Freescale Security Monitor block is responsible for monitoring
288 system states.
289 Security Monitor can be transitioned on any security failures,
290 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100291
Tom Rini0b58c2e2022-06-16 14:04:39 -0400292choice
293 prompt "Security monitor interaction endianess"
294 depends on FSL_SEC_MON
295 default SYS_FSL_SEC_MON_BE if PPC
296 default SYS_FSL_SEC_MON_LE
297
298config SYS_FSL_SEC_MON_LE
299 bool "Security monitor interactions are little endian"
300
301config SYS_FSL_SEC_MON_BE
302 bool "Security monitor interactions are big endian"
303
304endchoice
305
Simon Glassff418d92019-12-06 21:41:58 -0700306config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100307 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700308 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100309 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700310 Some devices have extra features, such as Apollo Lake. The
311 device has its own uclass since there are several operations
312 involved.
313
Paul Burton738d8a82018-12-16 19:25:19 -0300314config JZ4780_EFUSE
315 bool "Ingenic JZ4780 eFUSE support"
316 depends on ARCH_JZ47XX
317 help
318 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
319
Sean Anderson6b39d352022-04-22 14:34:18 -0400320config LS2_SFP
321 bool "Layerscape Security Fuse Processor"
322 depends on FSL_LSCH2 || ARCH_LS1021A
323 depends on MISC
324 imply DM_REGULATOR
325 help
326 This adds support for the Security Fuse Processor found on Layerscape
327 SoCs. It contains various fuses related to secure boot, including the
328 Super Root Key hash, One-Time-Programmable Master Key, Debug
329 Challenge/Response values, and others. Fuses are numbered according
330 to their four-byte offset from the start of the bank.
331
332 If you don't need to read/program fuses, say 'n'.
333
Peng Fane1872252015-08-27 14:49:05 +0800334config MXC_OCOTP
335 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000336 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100337 default y
Peng Fane1872252015-08-27 14:49:05 +0800338 help
339 If you say Y here, you will get support for the One Time
340 Programmable memory pages that are stored on the some
341 Freescale i.MX processors.
342
Tom Rini5a0f9d82022-11-19 18:45:28 -0500343config MXS_OCOTP
344 bool "Enable MXS OCOTP Driver"
345 depends on ARCH_MX23 || ARCH_MX28
346 help
347 If you say Y here, you will get support for the One Time
348 Programmable memory pages that are stored on the
349 Freescale i.MXS family of processors.
350
Jim Liucce4eed2022-06-24 16:24:37 +0800351config NPCM_HOST
352 bool "Enable support espi or LPC for Host"
353 depends on REGMAP && SYSCON
354 help
355 Enable NPCM BMC espi or LPC support for Host reading and writing.
356
Michael Scott92676142021-09-25 19:49:28 +0300357config SPL_MXC_OCOTP
358 bool "Enable MXC OCOTP driver in SPL"
Jean-Marie Lemetayerf17d43d2023-02-13 14:12:25 +0100359 depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300360 default y
361 help
362 If you say Y here, you will get support for the One Time
363 Programmable memory pages, that are stored on some
364 Freescale i.MX processors, in SPL.
365
Jim Liufab2eff2022-06-07 16:33:54 +0800366config NPCM_OTP
367 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
368 depends on (ARM && ARCH_NPCM)
369 default n
370 help
371 Support NPCM BMC OTP memory (fuse).
372 To compile this driver as a module, choose M here: the module
373 will be called npcm_otp.
374
Peng Fand5c31832023-06-15 18:09:05 +0800375config IMX_ELE
376 bool "Enable i.MX EdgeLock Enclave MU driver and API"
Ye Lic408ed32022-07-26 16:40:49 +0800377 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
378 help
379 If you say Y here to enable Message Unit driver to work with
380 Sentinel core on some NXP i.MX processors.
381
Stefan Roese4a269f22016-07-19 07:45:46 +0200382config NUVOTON_NCT6102D
383 bool "Enable Nuvoton NCT6102D Super I/O driver"
384 help
385 If you say Y here, you will get support for the Nuvoton
386 NCT6102D Super I/O driver. This can be used to enable or
387 disable the legacy UART, the watchdog or other devices
388 in the Nuvoton Super IO chips on X86 platforms.
389
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700390config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200391 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700392 depends on X86 || SANDBOX
393 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200394 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700395 abbreviated to P2SB. The P2SB is used to access various peripherals
396 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
397 space. The space is segmented into different channels and peripherals
398 are accessed by device-specific means within those channels. Devices
399 should be added in the device tree as subnodes of the P2SB. A
400 Peripheral Channel Register? (PCR) API is provided to access those
401 devices - see pcr_readl(), etc.
402
403config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200404 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400405 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700406 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200407 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700408 through memory-mapped I/O in a large chunk of PCI space. The space is
409 segmented into different channels and peripherals are accessed by
410 device-specific means within those channels. Devices should be added
411 in the device tree as subnodes of the p2sb.
412
413config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200414 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400415 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700416 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200417 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700418 through memory-mapped I/O in a large chunk of PCI space. The space is
419 segmented into different channels and peripherals are accessed by
420 device-specific means within those channels. Devices should be added
421 in the device tree as subnodes of the p2sb.
422
Simon Glassc9795172016-01-21 19:43:31 -0700423config PWRSEQ
424 bool "Enable power-sequencing drivers"
425 depends on DM
426 help
427 Power-sequencing drivers provide support for controlling power for
428 devices. They are typically referenced by a phandle from another
429 device. When the device is started up, its power sequence can be
430 initiated.
431
432config SPL_PWRSEQ
433 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400434 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700435 help
436 Power-sequencing drivers provide support for controlling power for
437 devices. They are typically referenced by a phandle from another
438 device. When the device is started up, its power sequence can be
439 initiated.
440
Stefan Roese04b22752015-03-12 11:22:46 +0100441config PCA9551_LED
442 bool "Enable PCA9551 LED driver"
443 help
444 Enable driver for PCA9551 LED controller. This controller
445 is connected via I2C. So I2C needs to be enabled.
446
447config PCA9551_I2C_ADDR
448 hex "I2C address of PCA9551 LED controller"
449 depends on PCA9551_LED
450 default 0x60
451 help
452 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600453
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200454config STM32MP_FUSE
455 bool "Enable STM32MP fuse wrapper providing the fuse API"
456 depends on ARCH_STM32MP && MISC
457 default y if CMD_FUSE
458 help
459 If you say Y here, you will get support for the fuse API (OTP)
460 for STM32MP architecture.
461 This API is needed for CMD_FUSE.
462
Christophe Kerello275f7062017-09-13 18:00:08 +0200463config STM32_RCC
464 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400465 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200466 help
467 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
468 block) is responsible of the management of the clock and reset
469 generation.
470 This driver is similar to an MFD driver in the Linux kernel.
471
Stephen Warrenf6417002016-09-13 10:45:57 -0600472config TEGRA_CAR
473 bool "Enable support for the Tegra CAR driver"
474 depends on TEGRA_NO_BPMP
475 help
476 The Tegra CAR (Clock and Reset Controller) is a HW module that
477 controls almost all clocks and resets in a Tegra SoC.
478
Stephen Warrena2148922016-08-08 09:41:34 -0600479config TEGRA186_BPMP
480 bool "Enable support for the Tegra186 BPMP driver"
481 depends on TEGRA186
482 help
483 The Tegra BPMP (Boot and Power Management Processor) is a separate
484 auxiliary CPU embedded into Tegra to perform power management work,
485 and controls related features such as clocks, resets, power domains,
486 PMIC I2C bus, etc. This driver provides the core low-level
487 communication path by which feature-specific drivers (such as clock)
488 can make requests to the BPMP. This driver is similar to an MFD
489 driver in the Linux kernel.
490
Simon Glass4bf89722020-12-23 08:11:18 -0700491config TEST_DRV
492 bool "Enable support for test drivers"
493 default y if SANDBOX
494 help
495 This enables drivers and uclasses that provides a way of testing the
496 operations of memory allocation and driver/uclass methods in driver
497 model. This should only be enabled for testing as it is not useful for
498 anything else.
499
Marek Vasut16637b42022-04-10 06:27:14 +0200500config USB_HUB_USB251XB
501 tristate "USB251XB Hub Controller Configuration Driver"
502 depends on I2C
503 help
504 This option enables support for configuration via SMBus of the
505 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
506 parameters may be set in devicetree or platform data.
507 Say Y or M here if you need to configure such a device via SMBus.
508
Adam Fordc8cdce72018-08-06 14:26:50 -0500509config TWL4030_LED
510 bool "Enable TWL4030 LED controller"
511 help
512 Enable this to add support for the TWL4030 LED controller.
513
Stefan Roeseba019ed2016-01-19 14:05:10 +0100514config WINBOND_W83627
515 bool "Enable Winbond Super I/O driver"
516 help
517 If you say Y here, you will get support for the Winbond
518 W83627 Super I/O driver. This can be used to enable the
519 legacy UART or other devices in the Winbond Super IO chips
520 on X86 platforms.
521
Vladimir Zapolskiyf7a64292023-04-21 20:50:33 +0300522config QCOM_GENI_SE
523 bool "Qualcomm GENI Serial Engine Driver"
524 depends on ARCH_SNAPDRAGON
525 help
526 The driver manages Generic Interface (GENI) firmware based
527 Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
528
Miao Yan4fcd7f22016-05-22 19:37:14 -0700529config QFW
530 bool
531 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100532 Hidden option to enable QEMU fw_cfg interface and uclass. This will
533 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
534
535config QFW_PIO
536 bool
537 depends on QFW
538 help
539 Hidden option to enable PIO QEMU fw_cfg interface. This will be
540 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700541
Asherah Connorf0c0e542021-03-19 18:21:42 +1100542config QFW_MMIO
543 bool
544 depends on QFW
545 help
546 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
547 selected by the appropriate QEMU board.
548
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200549config I2C_EEPROM
550 bool "Enable driver for generic I2C-attached EEPROMs"
551 depends on MISC
552 help
553 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500554
Wenyou Yangf791d562017-09-06 13:08:14 +0800555
556config SPL_I2C_EEPROM
557 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400558 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800559 help
560 This option is an SPL-variant of the I2C_EEPROM option.
561 See the help of I2C_EEPROM for details.
562
Adam Ford5664f832017-08-13 09:00:28 -0500563config SYS_I2C_EEPROM_ADDR
564 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400565 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Tom Rinif18679c2023-08-02 11:09:43 -0400566 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500567
Tom Rinifaed5672021-08-17 17:59:45 -0400568if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500569
570config SYS_I2C_EEPROM_ADDR_OVERFLOW
571 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500572 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500573 help
574 EEPROM chips that implement "address overflow" are ones
575 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
576 address and the extra bits end up in the "chip address" bit
577 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
578 byte chips.
579
580endif
581
Mario Six7f504a02018-04-27 14:53:33 +0200582config GDSYS_RXAUI_CTRL
583 bool "Enable gdsys RXAUI control driver"
584 depends on MISC
585 help
586 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200587
588config GDSYS_IOEP
589 bool "Enable gdsys IOEP driver"
590 depends on MISC
591 help
592 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200593
594config MPC83XX_SERDES
595 bool "Enable MPC83xx serdes driver"
596 depends on MISC
597 help
598 Support for serdes found on MPC83xx SoCs.
599
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800600config FS_LOADER
601 bool "Enable loader driver for file system"
602 help
603 This is file system generic loader which can be used to load
604 the file image from the storage into target such as memory.
605
606 The consumer driver would then use this loader to program whatever,
607 ie. the FPGA device.
608
Keerthyfe8f6092022-01-27 13:16:53 +0100609config SPL_FS_LOADER
610 bool "Enable loader driver for file system"
Tom Rini0f311f22022-05-10 12:51:47 -0400611 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100612 help
613 This is file system generic loader which can be used to load
614 the file image from the storage into target such as memory.
615
616 The consumer driver would then use this loader to program whatever,
617 ie. the FPGA device.
618
Mario Six8862f452018-10-04 09:00:54 +0200619config GDSYS_SOC
620 bool "Enable gdsys SOC driver"
621 depends on MISC
622 help
623 Support for gdsys IHS SOC, a simple bus associated with each gdsys
624 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
625 register maps are contained within the FPGA's register map.
626
Mario Six1a9d43f2018-10-04 09:00:55 +0200627config IHS_FPGA
628 bool "Enable IHS FPGA driver"
629 depends on MISC
630 help
631 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
632 gdsys devices, which supply the majority of the functionality offered
633 by the devices. This driver supports both CON and CPU variants of the
634 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200635config ESM_K3
636 bool "Enable K3 ESM driver"
637 depends on ARCH_K3
638 help
639 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200640
Eugen Hristev3bd56102019-10-09 09:23:39 +0000641config MICROCHIP_FLEXCOM
642 bool "Enable Microchip Flexcom driver"
643 depends on MISC
644 help
645 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
646 an I2C controller and an USART.
647 Only one function can be used at a time and is chosen at boot time
648 according to the device tree.
649
Tero Kristo887dde52019-10-24 15:00:46 +0530650config K3_AVS0
651 depends on ARCH_K3 && SPL_DM_REGULATOR
652 bool "AVS class 0 support for K3 devices"
653 help
654 K3 devices have the optimized voltage values for the main voltage
655 domains stored in efuse within the VTM IP. This driver reads the
656 optimized voltage from the efuse, so that it can be programmed
657 to the PMIC on board.
658
Tero Kristo1444e112020-02-14 11:18:16 +0200659config ESM_PMIC
660 bool "Enable PMIC ESM driver"
661 depends on DM_PMIC
662 help
663 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
664 typically to reboot the board in error condition.
665
Tom Rini05b419e2021-12-11 14:55:49 -0500666config FSL_IFC
667 bool
668
Michael Walle2184cc62022-02-25 18:06:24 +0530669config SL28CPLD
670 bool "Enable Kontron sl28cpld multi-function driver"
671 depends on DM_I2C
672 help
673 Support for the Kontron sl28cpld management controller. This is
674 the base driver which provides common access methods for the
675 sub-drivers.
676
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900677endmenu