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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephen Warrena69a33d2012-05-16 13:54:07 +00002/*
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
Stephen Warrena69a33d2012-05-16 13:54:07 +00005 */
6
Stephen Warrena69a33d2012-05-16 13:54:07 +00007#include <asm/io.h>
Tom Warrenab371962012-09-19 15:50:56 -07008#include <asm/arch/tegra.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +00009#include <asm/arch/clock.h>
10#include <asm/arch/funcmux.h>
11#include <asm/arch/pinmux.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +000012#include <asm/gpio.h>
Tom Warrenab371962012-09-19 15:50:56 -070013#include <i2c.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +000014
Stephen Warrendbe5bb52012-11-01 12:14:37 +000015void pin_mux_usb(void)
16{
17 /*
18 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
19 * in the current device tree.
20 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -060021 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Stephen Warrendbe5bb52012-11-01 12:14:37 +000022}
Stephen Warrena69a33d2012-05-16 13:54:07 +000023
Stephen Warren85acaba2012-06-12 08:33:41 +000024void pin_mux_spi(void)
25{
26 funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
27}
28
Stephen Warrena69a33d2012-05-16 13:54:07 +000029/*
30 * Routine: pin_mux_mmc
31 * Description: setup the pin muxes/tristate values for the SDMMC(s)
32 */
Tom Warren9745cf82013-02-21 12:31:30 +000033void pin_mux_mmc(void)
Stephen Warrena69a33d2012-05-16 13:54:07 +000034{
35 funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
36 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
37
38 /* For CD GPIO PP1 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -060039 pinmux_tristate_disable(PMUX_PINGRP_DAP3);
Stephen Warrena69a33d2012-05-16 13:54:07 +000040}