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Stephen Warrena69a33d2012-05-16 13:54:07 +00001/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stephen Warrena69a33d2012-05-16 13:54:07 +00006 */
7
8#include <common.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +00009#include <asm/io.h>
Tom Warrenab371962012-09-19 15:50:56 -070010#include <asm/arch/tegra.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +000011#include <asm/arch/clock.h>
12#include <asm/arch/funcmux.h>
13#include <asm/arch/pinmux.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +000014#include <asm/gpio.h>
Tom Warrenab371962012-09-19 15:50:56 -070015#include <i2c.h>
Stephen Warrena69a33d2012-05-16 13:54:07 +000016
Stephen Warrendbe5bb52012-11-01 12:14:37 +000017void pin_mux_usb(void)
18{
19 /*
20 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
21 * in the current device tree.
22 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -060023 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Stephen Warrendbe5bb52012-11-01 12:14:37 +000024}
Stephen Warrena69a33d2012-05-16 13:54:07 +000025
Stephen Warren85acaba2012-06-12 08:33:41 +000026void pin_mux_spi(void)
27{
28 funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
29}
30
Stephen Warrena69a33d2012-05-16 13:54:07 +000031/*
32 * Routine: pin_mux_mmc
33 * Description: setup the pin muxes/tristate values for the SDMMC(s)
34 */
Tom Warren9745cf82013-02-21 12:31:30 +000035void pin_mux_mmc(void)
Stephen Warrena69a33d2012-05-16 13:54:07 +000036{
37 funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
38 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
39
40 /* For CD GPIO PP1 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -060041 pinmux_tristate_disable(PMUX_PINGRP_DAP3);
Stephen Warrena69a33d2012-05-16 13:54:07 +000042}