blob: 391d973c0b6d045b4f67625fb1681deddcaf7042 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass9d5d1cc2015-08-30 16:55:42 -06002/*
3 * (C) Copyright 2015 Google, Inc
Simon Glass9d5d1cc2015-08-30 16:55:42 -06004 */
5
Kever Yang71195ce2019-07-22 20:02:12 +08006#include <clk.h>
Simon Glass9d5d1cc2015-08-30 16:55:42 -06007#include <common.h>
Kever Yang71195ce2019-07-22 20:02:12 +08008#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Kever Yang92471042019-07-22 20:02:11 +080011#include <asm/arch-rockchip/clock.h>
Kever Yang71195ce2019-07-22 20:02:12 +080012#include <dt-bindings/clock/rk3288-cru.h>
Simon Glassdbd79542020-05-10 11:40:11 -060013#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070014#include <linux/err.h>
Kever Yang71195ce2019-07-22 20:02:12 +080015#include <power/regulator.h>
Simon Glass57538b32016-11-13 14:22:11 -070016
17/*
18 * We should increase the DDR voltage to 1.2V using the PWM regulator.
19 * There is a U-Boot driver for this but it may need to add support for the
20 * 'voltage-table' property.
21 */
Kever Yang71195ce2019-07-22 20:02:12 +080022#ifndef CONFIG_SPL_BUILD
23#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
24static int veyron_init(void)
25{
26 struct udevice *dev;
27 struct clk clk;
28 int ret;
29
30 ret = regulator_get_by_platname("vdd_arm", &dev);
31 if (ret) {
32 debug("Cannot set regulator name\n");
33 return ret;
34 }
35
36 /* Slowly raise to max CPU voltage to prevent overshoot */
37 ret = regulator_set_value(dev, 1200000);
38 if (ret)
39 return ret;
40 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
41 ret = regulator_set_value(dev, 1400000);
42 if (ret)
43 return ret;
44 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
45
46 ret = rockchip_get_clk(&clk.dev);
47 if (ret)
48 return ret;
49 clk.id = PLL_APLL;
50 ret = clk_set_rate(&clk, 1800000000);
51 if (IS_ERR_VALUE(ret))
52 return ret;
53
54 ret = regulator_get_by_platname("vcc33_sd", &dev);
55 if (ret) {
56 debug("Cannot get regulator name\n");
57 return ret;
58 }
59
60 ret = regulator_set_value(dev, 3300000);
61 if (ret)
62 return ret;
63
64 ret = regulators_enable_boot_on(false);
65 if (ret) {
66 debug("%s: Cannot enable boot on regulators\n", __func__);
67 return ret;
68 }
69
70 return 0;
71}
72#endif
Kever Yang92471042019-07-22 20:02:11 +080073
Urja Rannikkoe8c4c962020-05-13 19:15:21 +000074int board_early_init_r(void)
Kever Yang92471042019-07-22 20:02:11 +080075{
76 struct udevice *dev;
77 int ret;
78
Kever Yang71195ce2019-07-22 20:02:12 +080079#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
80 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
81 ret = veyron_init();
82 if (ret)
83 return ret;
84 }
85#endif
Kever Yang92471042019-07-22 20:02:11 +080086 /*
87 * This init is done in SPL, but when chain-loading U-Boot SPL will
88 * have been skipped. Allow the clock driver to check if it needs
89 * setting up.
90 */
91 ret = rockchip_get_clk(&dev);
92 if (ret) {
93 debug("CLK init failed: %d\n", ret);
94 return ret;
95 }
96
97 return 0;
98}
Kever Yang71195ce2019-07-22 20:02:12 +080099#endif