blob: 02bc5ed37bbae36d00c58e7dd0f9635a746254b2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass9d5d1cc2015-08-30 16:55:42 -06002/*
3 * (C) Copyright 2015 Google, Inc
Simon Glass9d5d1cc2015-08-30 16:55:42 -06004 */
5
Kever Yang71195ce2019-07-22 20:02:12 +08006#include <clk.h>
Simon Glass9d5d1cc2015-08-30 16:55:42 -06007#include <common.h>
Kever Yang71195ce2019-07-22 20:02:12 +08008#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Kever Yang92471042019-07-22 20:02:11 +080011#include <asm/arch-rockchip/clock.h>
Kever Yang71195ce2019-07-22 20:02:12 +080012#include <dt-bindings/clock/rk3288-cru.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070013#include <linux/err.h>
Kever Yang71195ce2019-07-22 20:02:12 +080014#include <power/regulator.h>
Simon Glass57538b32016-11-13 14:22:11 -070015
16/*
17 * We should increase the DDR voltage to 1.2V using the PWM regulator.
18 * There is a U-Boot driver for this but it may need to add support for the
19 * 'voltage-table' property.
20 */
Kever Yang71195ce2019-07-22 20:02:12 +080021#ifndef CONFIG_SPL_BUILD
22#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
23static int veyron_init(void)
24{
25 struct udevice *dev;
26 struct clk clk;
27 int ret;
28
29 ret = regulator_get_by_platname("vdd_arm", &dev);
30 if (ret) {
31 debug("Cannot set regulator name\n");
32 return ret;
33 }
34
35 /* Slowly raise to max CPU voltage to prevent overshoot */
36 ret = regulator_set_value(dev, 1200000);
37 if (ret)
38 return ret;
39 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
40 ret = regulator_set_value(dev, 1400000);
41 if (ret)
42 return ret;
43 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
44
45 ret = rockchip_get_clk(&clk.dev);
46 if (ret)
47 return ret;
48 clk.id = PLL_APLL;
49 ret = clk_set_rate(&clk, 1800000000);
50 if (IS_ERR_VALUE(ret))
51 return ret;
52
53 ret = regulator_get_by_platname("vcc33_sd", &dev);
54 if (ret) {
55 debug("Cannot get regulator name\n");
56 return ret;
57 }
58
59 ret = regulator_set_value(dev, 3300000);
60 if (ret)
61 return ret;
62
63 ret = regulators_enable_boot_on(false);
64 if (ret) {
65 debug("%s: Cannot enable boot on regulators\n", __func__);
66 return ret;
67 }
68
69 return 0;
70}
71#endif
Kever Yang92471042019-07-22 20:02:11 +080072
73int board_early_init_f(void)
74{
75 struct udevice *dev;
76 int ret;
77
Kever Yang71195ce2019-07-22 20:02:12 +080078#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
79 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
80 ret = veyron_init();
81 if (ret)
82 return ret;
83 }
84#endif
Kever Yang92471042019-07-22 20:02:11 +080085 /*
86 * This init is done in SPL, but when chain-loading U-Boot SPL will
87 * have been skipped. Allow the clock driver to check if it needs
88 * setting up.
89 */
90 ret = rockchip_get_clk(&dev);
91 if (ret) {
92 debug("CLK init failed: %d\n", ret);
93 return ret;
94 }
95
96 return 0;
97}
Kever Yang71195ce2019-07-22 20:02:12 +080098#endif