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git01.mediatek.com / filogic / uboot / c3dc99f2cd71c948a14f1baf6ee347ede220c525 / . / arch / x86 / dts / qemu-x86_q35.dts
blob: e8f55b19a26291b5e51ebc70fbcd655fe0fd1693 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]2/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]4 */
5
6/dts-v1/;
7
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]8#include <dt-bindings/interrupt-router/intel-irq.h>
9
10/* ICH9 IRQ router has discrete PIRQ control registers */
11#undef PIRQE
12#undef PIRQF
13#undef PIRQG
14#undef PIRQH
15#define PIRQE 8
16#define PIRQF 9
17#define PIRQG 10
18#define PIRQH 11
19
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]20/include/ "skeleton.dtsi"
21/include/ "serial.dtsi"
Bin Meng7ca73742015-11-12 05:33:06 -0800[diff] [blame]22/include/ "keyboard.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]23/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]24/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]25/include/ "tsc_timer.dtsi"
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]26
27/ {
Bin Meng000883b2015-06-03 09:20:04 +0800[diff] [blame]28 model = "QEMU x86 (Q35)";
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]29 compatible = "qemu,x86";
30
31 config {
32 silent_console = <0>;
Bin Meng70be0962015-06-03 09:20:05 +0800[diff] [blame]33 u-boot,no-apm-finalize;
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]34 };
35
36 chosen {
37 stdout-path = "/serial";
38 };
39
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]43 u-boot,dm-pre-reloc;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]44
45 cpu@0 {
46 device_type = "cpu";
Miao Yan4336af62016-01-07 01:32:01 -0800[diff] [blame]47 compatible = "cpu-qemu";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]48 u-boot,dm-pre-reloc;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]49 reg = <0>;
50 intel,apic-id = <0>;
51 };
52 };
53
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]54 tsc-timer {
55 clock-frequency = <1000000000>;
56 };
57
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]58 pci {
59 compatible = "pci-x86";
60 #address-cells = <3>;
61 #size-cells = <2>;
62 u-boot,dm-pre-reloc;
63 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
64 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
65 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]66
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]67 pch@1f,0 {
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]68 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]69 compatible = "intel,pch9";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]70 u-boot,dm-pre-reloc;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]71
72 irq-router {
73 compatible = "intel,irq-router";
Bin Menged3fd5b2017-01-18 03:32:57 -0800[diff] [blame]74 u-boot,dm-pre-reloc;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]75 intel,pirq-config = "pci";
Bin Meng0651f622016-05-07 07:46:15 -0700[diff] [blame]76 intel,actl-8bit;
77 intel,actl-addr = <0x44>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]78 intel,pirq-link = <0x60 8>;
79 intel,pirq-mask = <0x0e40>;
80 intel,pirq-routing = <
81 /* e1000 NIC */
82 PCI_BDF(0, 2, 0) INTA PIRQG
83 /* ICH9 UHCI */
84 PCI_BDF(0, 29, 0) INTA PIRQA
85 PCI_BDF(0, 29, 1) INTB PIRQB
86 PCI_BDF(0, 29, 2) INTC PIRQC
87 /* ICH9 EHCI */
88 PCI_BDF(0, 29, 7) INTD PIRQD
89 /* ICH9 SATA */
90 PCI_BDF(0, 31, 2) INTA PIRQA
91 >;
92 };
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]93 };
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]94 };
95
96};