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git01.mediatek.com / filogic / uboot / c3d9e3d79d6a275fb964ae8a68cfbefeccc5d638 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 3fa18f560c9cb100d82bba5779b14205c7f0b7b5 [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]27 nvmem1 = &eeprom_ebm;
28 nvmem2 = &eeprom_fmc1;
29 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &dcc;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
44
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]45 si5332_1: si5332_1 { /* u142 - GEM0 */
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 };
50
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]51 ina226-vccint {
52 compatible = "iio-hwmon";
53 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
54 };
55 ina226-vcc-soc {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
58 };
59 ina226-vcc-pmc {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
62 };
63 ina226-vcc-ram {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
66 };
67 ina226-vcc-pslp {
68 compatible = "iio-hwmon";
69 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
70 };
71 ina226-vcc-psfp {
72 compatible = "iio-hwmon";
73 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
74 };
75 ina226-vccaux {
76 compatible = "iio-hwmon";
77 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
78 };
79 ina226-vccaux-pmc {
80 compatible = "iio-hwmon";
81 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
82 };
83 ina226-vcco-500 {
84 compatible = "iio-hwmon";
85 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
86 };
87 ina226-vcco-501 {
88 compatible = "iio-hwmon";
89 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
90 };
91 ina226-vcco-502 {
92 compatible = "iio-hwmon";
93 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
94 };
95 ina226-vcco-503 {
96 compatible = "iio-hwmon";
97 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
98 };
99 ina226-vcc-1v8 {
100 compatible = "iio-hwmon";
101 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
102 };
103 ina226-vcc-3v3 {
104 compatible = "iio-hwmon";
105 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
106 };
107 ina226-vcc-1v2-ddr4 {
108 compatible = "iio-hwmon";
109 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
110 };
111 ina226-vcc-1v1-lp4 {
112 compatible = "iio-hwmon";
113 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
114 };
115 ina226-vadj-fmc {
116 compatible = "iio-hwmon";
117 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
118 };
119 ina226-mgtyavcc {
120 compatible = "iio-hwmon";
121 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
122 };
123 ina226-mgtyavtt {
124 compatible = "iio-hwmon";
125 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
126 };
127 ina226-mgtyvccaux {
128 compatible = "iio-hwmon";
129 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
130 };
131};
132
133&uart0 { /* uart0 MIO38-39 */
134 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]135};
136
137&sdhci1 { /* sd1 MIO45-51 cd in place */
138 status = "okay";
139 no-1-8-v;
140 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]141 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]142};
143
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]144/* GEM SGMII */
145&psgtr {
146 status = "okay";
147 /* gem0 */
148 clocks = <&si5332_1>;
149 clock-names = "ref0";
150};
151
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]152&gem0 {
153 status = "okay";
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]154 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]155 phy-handle = <&phy0>;
156 phy-mode = "sgmii";
157 is-internal-pcspma;
Michal Simek8acb6b72022-09-06 12:39:11 +0200[diff] [blame]158 mdio: mdio {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 phy0: ethernet-phy@0 { /* u131 M88E1512 */
162 reg = <0>;
163 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]164 };
165};
166
167&gpio {
168 status = "okay";
169 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
170 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
171 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
172 "", "", "", "", "", /* 15 - 19 */
173 "", "", "", "", "", /* 20 - 24 */
174 "", "", "", "", "", /* 25 - 29 */
175 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
176 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
177 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
178 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
179 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
180 "", "", "", "", "", /* 55 - 59 */
181 "", "", "", "", "", /* 60 - 64 */
182 "", "", "", "", "", /* 65 - 69 */
183 "", "", "", "", "", /* 70 - 74 */
184 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]185 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]186 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
187 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
188 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
189 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]190 "", "", "", "", "", /* 100 - 104 */
191 "", "", "", "", "", /* 105 - 109 */
192 "", "", "", "", "", /* 110 - 114 */
193 "", "", "", "", "", /* 115 - 119 */
194 "", "", "", "", "", /* 120 - 124 */
195 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]196 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]197 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]198 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
199 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]200 "", "", "", "", "", /* 150 - 154 */
201 "", "", "", "", "", /* 155 - 159 */
202 "", "", "", "", "", /* 160 - 164 */
203 "", "", "", "", "", /* 165 - 169 */
204 "", "", "", ""; /* 170 - 174 */
205};
206
207&i2c0 { /* MIO 34-35 - can't stay here */
208 status = "okay";
209 clock-frequency = <400000>;
Michal Simeka43fdcd2022-08-23 15:00:25 +0200[diff] [blame]210
211 tca6416_u233: gpio@20 { /* u233 */
212 compatible = "ti,tca6416";
213 reg = <0x20>;
214 gpio-controller; /* interrupt not connected */
215 #gpio-cells = <2>;
216 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
217 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */
218 "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */
219 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
220 };
221
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]222 i2c-mux@74 { /* u33 */
223 compatible = "nxp,pca9548";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x74>;
227 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
228 i2c@0 { /* PMBUS */
229 #address-cells = <1>;
230 #size-cells = <0>;
231 reg = <0>;
232 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]233 /* u179 ir38164 0x19/0x49 vcco_500 */
234 /* u181 ir38164 0x1a/0x4a vcco_501 */
235 /* u183 ir38164 0x1b/0x4b vcco_502 */
236 /* u185 ir38164 0x1e/0x4e vadj_fmc */
237 /* u187 ir38164 0x1F/0x4f mgtyavcc */
238 /* u189 ir38164 0x20/0x50 mgtyavtt */
239 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
240 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]241
242 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
243 compatible = "infineon,irps5401";
244 reg = <0x47>; /* pmbus / i2c 0x17 */
245 };
246 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
247 compatible = "infineon,irps5401";
248 reg = <0x4c>; /* pmbus / i2c 0x1c */
249 };
250 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
251 compatible = "infineon,irps5401";
252 reg = <0x4d>; /* pmbus / i2c 0x1d */
253 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]254 };
255 i2c@1 { /* PMBUS1_INA226 */
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <1>;
259 /* FIXME check alerts coming to SC */
260 vccint: ina226@40 { /* u65 */
261 compatible = "ti,ina226";
262 #io-channel-cells = <1>;
263 label = "ina226-vccint";
264 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]265 shunt-resistor = <500>; /* R440 */
266 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]267 };
268 vcc_soc: ina226@41 { /* u161 */
269 compatible = "ti,ina226";
270 #io-channel-cells = <1>;
271 label = "ina226-vcc-soc";
272 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]273 shunt-resistor = <500>; /* R1702 */
274 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]275 };
276 vcc_pmc: ina226@42 { /* u163 */
277 compatible = "ti,ina226";
278 #io-channel-cells = <1>;
279 label = "ina226-vcc-pmc";
280 reg = <0x42>;
281 shunt-resistor = <5000>; /* R1214 */
282 /* 0.78V @ 500mA */
283 };
284 vcc_ram: ina226@43 { /* u162 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-vcc-ram";
288 reg = <0x43>;
289 shunt-resistor = <5000>; /* r1221 */
290 /* 0.78V @ 4A */
291 };
292 vcc_pslp: ina226@44 { /* u165 */
293 compatible = "ti,ina226";
294 #io-channel-cells = <1>;
295 label = "ina226-vcc-pslp";
296 reg = <0x44>;
297 shunt-resistor = <5000>; /* R1216 */
298 /* 0.78V @ 1A */
299 };
300 vcc_psfp: ina226@45 { /* u164 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 label = "ina226-vcc-psfp";
304 reg = <0x45>;
305 shunt-resistor = <5000>; /* R1219 */
306 /* 0.78V @ 2A */
307 };
308 };
309 i2c@2 { /* PCIE_CLK */
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <2>;
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]313 clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]314 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
315 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]316 reg = <0x6c>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]317 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
318 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
319 };
320 };
321 i2c@3 { /* PMBUS2_INA226 */
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <3>;
325 /* FIXME check alerts coming to SC */
326 vccaux: ina226@40 { /* u166 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-vccaux";
330 reg = <0x40>;
331 shunt-resistor = <5000>; /* R382 */
332 /* 1.5V @ 3A */
333 };
334 vccaux_pmc: ina226@41 { /* u168 */
335 compatible = "ti,ina226";
336 #io-channel-cells = <1>;
337 label = "ina226-vccaux-pmc";
338 reg = <0x41>;
339 shunt-resistor = <5000>; /* R1246 */
340 /* 1.5V @ 500mA */
341 };
342 vcco_500: ina226@42 { /* u178 */
343 compatible = "ti,ina226";
344 #io-channel-cells = <1>;
345 label = "ina226-vcco-500";
346 reg = <0x42>;
347 shunt-resistor = <2000>; /* R1300 */
348 /* 3.3V @ 5A */
349 };
350 vcco_501: ina226@43 { /* u180 */
351 compatible = "ti,ina226";
352 #io-channel-cells = <1>;
353 label = "ina226-vcco-501";
354 reg = <0x43>;
355 shunt-resistor = <2000>; /* R1313 */
356 /* 3.3V @ 5A */
357 };
358 vcco_502: ina226@44 { /* u182 */
359 compatible = "ti,ina226";
360 #io-channel-cells = <1>;
361 label = "ina226-vcco-502";
362 reg = <0x44>;
363 shunt-resistor = <2000>; /* R1330 */
364 /* 3.3V @ 5A */
365 };
366 vcco_503: ina226@45 { /* u172 */
367 compatible = "ti,ina226";
368 #io-channel-cells = <1>;
369 label = "ina226-vcco-503";
370 reg = <0x45>;
371 shunt-resistor = <5000>; /* R1229 */
372 /* 1.8V @ 2A */
373 };
374 vcc_1v8: ina226@46 { /* u173 */
375 compatible = "ti,ina226";
376 #io-channel-cells = <1>;
377 label = "ina226-vcc-1v8";
378 reg = <0x46>;
379 shunt-resistor = <5000>; /* R400 */
380 /* 1.8V @ 6A */
381 };
382 vcc_3v3: ina226@47 { /* u174 */
383 compatible = "ti,ina226";
384 #io-channel-cells = <1>;
385 label = "ina226-vcc-3v3";
386 reg = <0x47>;
387 shunt-resistor = <5000>; /* R1232 */
388 /* 3.3V @ 500mA */
389 };
390 vcc_1v2_ddr4: ina226@48 { /* u176 */
391 compatible = "ti,ina226";
392 #io-channel-cells = <1>;
393 label = "ina226-vcc-1v2-ddr4";
394 reg = <0x48>;
395 shunt-resistor = <5000>; /* R1275 */
396 /* 1.2V @ 4A */
397 };
398 vcc1v1_lp4: ina226@49 { /* u177 */
399 compatible = "ti,ina226";
400 #io-channel-cells = <1>;
401 label = "ina226-vcc1v1-lp4";
402 reg = <0x49>;
403 shunt-resistor = <5000>; /* R1286 */
404 /* 1.1V @ 4A */
405 };
406 vadj_fmc: ina226@4a { /* u184 */
407 compatible = "ti,ina226";
408 #io-channel-cells = <1>;
409 label = "ina226-vadj-fmc";
410 reg = <0x4a>;
411 shunt-resistor = <2000>; /* R1350 */
412 /* 1.5V @ 10A */
413 };
414 mgtyavcc: ina226@4b { /* u186 */
415 compatible = "ti,ina226";
416 #io-channel-cells = <1>;
417 label = "ina226-mgtyavcc";
418 reg = <0x4b>;
419 shunt-resistor = <2000>; /* R1367 */
420 /* 0.88V @ 6A */
421 };
422 mgtyavtt: ina226@4c { /* u188 */
423 compatible = "ti,ina226";
424 #io-channel-cells = <1>;
425 label = "ina226-mgtyavtt";
426 reg = <0x4c>;
427 shunt-resistor = <2000>; /* R1384 */
428 /* 1.2V @ 10A */
429 };
430 mgtyvccaux: ina226@4d { /* u234 */
431 compatible = "ti,ina226";
432 #io-channel-cells = <1>;
433 label = "ina226-mgtyvccaux";
434 reg = <0x4d>;
435 shunt-resistor = <5000>; /* r1679 */
436 /* 1.5V @ 500mA */
437 };
438 };
439 i2c@4 { /* LP_I2C_SM */
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <4>;
443 /* FIXME wires ready but chip is missing */
444 };
445 i2c@5 { /* zSFP_SI570 */
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <5>;
449 si570_zsfp: clock-generator@5d { /* u192 */
450 #clock-cells = <0>;
451 compatible = "silabs,si570";
452 reg = <0x5d>;
453 temperature-stability = <50>;
454 factory-fout = <156250000>;
455 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]456 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]457 };
458 };
459 i2c@6 { /* USER_SI570_1 */
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]463 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]464 #clock-cells = <0>;
465 compatible = "silabs,si570";
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]466 reg = <0x5d>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]467 temperature-stability = <50>;
468 factory-fout = <100000000>;
469 clock-frequency = <100000000>;
470 clock-output-names = "si570_user1";
471 };
472
473 };
474 i2c@7 { /* USER_SI570_2 */
475 #address-cells = <1>;
476 #size-cells = <0>;
477 reg = <7>;
478 /* FIXME wires ready but chip is missing */
479 };
480 };
481};
482
483&i2c1 { /* i2c1 MIO 36-37 */
484 status = "okay";
485 clock-frequency = <400000>;
486
487 i2c-mux@74 { /* u35 */
488 compatible = "nxp,pca9548";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]492 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]493 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
494 dc_i2c: i2c@0 { /* DC_I2C */
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <0>;
498 /* Use for storing information about SC board */
499 eeprom: eeprom@54 { /* u34 - m24128 16kB */
500 compatible = "st,24c128", "atmel,24c128";
501 reg = <0x54>; /* 0x5c too */
502 };
503 si570_ref_clk: clock-generator@5d { /* u32 */
504 #clock-cells = <0>;
505 compatible = "silabs,si570";
506 reg = <0x5d>;
507 temperature-stability = <50>;
508 factory-fout = <33333333>;
509 clock-frequency = <33333333>;
510 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]511 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]512 };
513 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]514 eeprom_ebm: eeprom@52 { /* x-ebm module */
515 compatible = "st,24c128", "atmel,24c128";
516 reg = <0x52>;
517 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]518 };
519 fmc1: i2c@1 { /* FMCP1_IIC */
520 #address-cells = <1>;
521 #size-cells = <0>;
522 reg = <1>;
523 /* FIXME connection to Samtec J51C */
524 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]525 eeprom_fmc1: eeprom@50 {
526 compatible = "st,24c128", "atmel,24c128";
527 reg = <0x50>;
528 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]529 };
530 fmc2: i2c@2 { /* FMCP2_IIC */
531 #address-cells = <1>;
532 #size-cells = <0>;
533 reg = <2>;
534 /* FIXME connection to Samtec J53C */
535 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]536 eeprom_fmc2: eeprom@50 {
537 compatible = "st,24c128", "atmel,24c128";
538 reg = <0x50>;
539 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]540 };
541 i2c@3 { /* DDR4_DIMM1 */
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <3>;
545 si570_ddr_dimm1: clock-generator@60 { /* u2 */
546 #clock-cells = <0>;
547 compatible = "silabs,si570";
548 reg = <0x60>;
549 temperature-stability = <50>;
550 factory-fout = <200000000>;
551 clock-frequency = <200000000>;
552 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]553 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]554 };
555 };
556 i2c@4 { /* LPDDR4_SI570_CLK2 */
557 #address-cells = <1>;
558 #size-cells = <0>;
559 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]560 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]561 #clock-cells = <0>;
562 compatible = "silabs,si570";
563 reg = <0x60>;
564 temperature-stability = <50>;
565 factory-fout = <200000000>;
566 clock-frequency = <200000000>;
567 clock-output-names = "si570_lpddr4_clk2";
568 };
569 };
570 i2c@5 { /* LPDDR4_SI570_CLK1 */
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]574 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]575 #clock-cells = <0>;
576 compatible = "silabs,si570";
577 reg = <0x60>;
578 temperature-stability = <50>;
579 factory-fout = <200000000>;
580 clock-frequency = <200000000>;
581 clock-output-names = "si570_lpddr4_clk1";
582 };
583 };
584 i2c@6 { /* HSDP_SI570 */
585 #address-cells = <1>;
586 #size-cells = <0>;
587 reg = <6>;
588 si570_hsdp: clock-generator@5d { /* u5 */
589 #clock-cells = <0>;
590 compatible = "silabs,si570";
591 reg = <0x5d>;
592 temperature-stability = <50>;
593 factory-fout = <156250000>;
594 clock-frequency = <156250000>;
595 clock-output-names = "si570_hsdp_clk";
596 };
597 };
598 i2c@7 { /* 8A34001 - U219B and J310 connector */
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <7>;
602 };
603 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]604 i2c-mux@75 { /* u214 */
605 compatible = "nxp,pca9548";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]609 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]610 i2c@0 { /* SFP0_IIC */
611 #address-cells = <1>;
612 #size-cells = <0>;
613 reg = <0>;
614 /* SFP0 */
615 };
616 i2c@1 { /* SFP1_IIC */
617 #address-cells = <1>;
618 #size-cells = <0>;
619 reg = <1>;
620 /* SFP1 */
621 };
622 i2c@2 { /* QSFP1_I2C */
623 #address-cells = <1>;
624 #size-cells = <0>;
625 reg = <2>;
626 /* QSFP1 */
627 };
628 /* 3 - 7 unused */
629 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]630};
631
632&xilinx_ams {
633 status = "okay";
634};
635
636&ams_ps {
637 status = "okay";
638};
639
640&ams_pl {
641 status = "okay";
642};