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git01.mediatek.com / filogic / uboot / a43fdcde488846d4f19a9bf6b30305f7a6585ff0 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 4940825b002f6a17f97a165c3810b7b8db3c358c [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]27 nvmem1 = &eeprom_ebm;
28 nvmem2 = &eeprom_fmc1;
29 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &dcc;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
44
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]45 si5332_1: si5332_1 { /* u142 - GEM0 */
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 };
50
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]51 ina226-vccint {
52 compatible = "iio-hwmon";
53 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
54 };
55 ina226-vcc-soc {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
58 };
59 ina226-vcc-pmc {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
62 };
63 ina226-vcc-ram {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
66 };
67 ina226-vcc-pslp {
68 compatible = "iio-hwmon";
69 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
70 };
71 ina226-vcc-psfp {
72 compatible = "iio-hwmon";
73 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
74 };
75 ina226-vccaux {
76 compatible = "iio-hwmon";
77 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
78 };
79 ina226-vccaux-pmc {
80 compatible = "iio-hwmon";
81 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
82 };
83 ina226-vcco-500 {
84 compatible = "iio-hwmon";
85 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
86 };
87 ina226-vcco-501 {
88 compatible = "iio-hwmon";
89 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
90 };
91 ina226-vcco-502 {
92 compatible = "iio-hwmon";
93 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
94 };
95 ina226-vcco-503 {
96 compatible = "iio-hwmon";
97 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
98 };
99 ina226-vcc-1v8 {
100 compatible = "iio-hwmon";
101 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
102 };
103 ina226-vcc-3v3 {
104 compatible = "iio-hwmon";
105 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
106 };
107 ina226-vcc-1v2-ddr4 {
108 compatible = "iio-hwmon";
109 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
110 };
111 ina226-vcc-1v1-lp4 {
112 compatible = "iio-hwmon";
113 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
114 };
115 ina226-vadj-fmc {
116 compatible = "iio-hwmon";
117 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
118 };
119 ina226-mgtyavcc {
120 compatible = "iio-hwmon";
121 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
122 };
123 ina226-mgtyavtt {
124 compatible = "iio-hwmon";
125 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
126 };
127 ina226-mgtyvccaux {
128 compatible = "iio-hwmon";
129 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
130 };
131};
132
133&uart0 { /* uart0 MIO38-39 */
134 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]135};
136
137&sdhci1 { /* sd1 MIO45-51 cd in place */
138 status = "okay";
139 no-1-8-v;
140 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]141 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]142};
143
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]144/* GEM SGMII */
145&psgtr {
146 status = "okay";
147 /* gem0 */
148 clocks = <&si5332_1>;
149 clock-names = "ref0";
150};
151
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]152&gem0 {
153 status = "okay";
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]154 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]155 phy-handle = <&phy0>;
156 phy-mode = "sgmii";
157 is-internal-pcspma;
158 phy0: ethernet-phy@0 { /* u131 M88E1512 */
159 reg = <0>;
160 };
161};
162
163&gpio {
164 status = "okay";
165 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
166 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
167 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
168 "", "", "", "", "", /* 15 - 19 */
169 "", "", "", "", "", /* 20 - 24 */
170 "", "", "", "", "", /* 25 - 29 */
171 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
172 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
173 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
174 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
175 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
176 "", "", "", "", "", /* 55 - 59 */
177 "", "", "", "", "", /* 60 - 64 */
178 "", "", "", "", "", /* 65 - 69 */
179 "", "", "", "", "", /* 70 - 74 */
180 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]181 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]182 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
183 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
184 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
185 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]186 "", "", "", "", "", /* 100 - 104 */
187 "", "", "", "", "", /* 105 - 109 */
188 "", "", "", "", "", /* 110 - 114 */
189 "", "", "", "", "", /* 115 - 119 */
190 "", "", "", "", "", /* 120 - 124 */
191 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]192 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]193 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]194 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
195 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]196 "", "", "", "", "", /* 150 - 154 */
197 "", "", "", "", "", /* 155 - 159 */
198 "", "", "", "", "", /* 160 - 164 */
199 "", "", "", "", "", /* 165 - 169 */
200 "", "", "", ""; /* 170 - 174 */
201};
202
203&i2c0 { /* MIO 34-35 - can't stay here */
204 status = "okay";
205 clock-frequency = <400000>;
Michal Simeka43fdcd2022-08-23 15:00:25 +0200[diff] [blame^]206
207 tca6416_u233: gpio@20 { /* u233 */
208 compatible = "ti,tca6416";
209 reg = <0x20>;
210 gpio-controller; /* interrupt not connected */
211 #gpio-cells = <2>;
212 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
213 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */
214 "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */
215 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
216 };
217
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]218 i2c-mux@74 { /* u33 */
219 compatible = "nxp,pca9548";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 reg = <0x74>;
223 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
224 i2c@0 { /* PMBUS */
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <0>;
228 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]229 /* u179 ir38164 0x19/0x49 vcco_500 */
230 /* u181 ir38164 0x1a/0x4a vcco_501 */
231 /* u183 ir38164 0x1b/0x4b vcco_502 */
232 /* u185 ir38164 0x1e/0x4e vadj_fmc */
233 /* u187 ir38164 0x1F/0x4f mgtyavcc */
234 /* u189 ir38164 0x20/0x50 mgtyavtt */
235 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
236 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]237
238 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
239 compatible = "infineon,irps5401";
240 reg = <0x47>; /* pmbus / i2c 0x17 */
241 };
242 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
243 compatible = "infineon,irps5401";
244 reg = <0x4c>; /* pmbus / i2c 0x1c */
245 };
246 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
247 compatible = "infineon,irps5401";
248 reg = <0x4d>; /* pmbus / i2c 0x1d */
249 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]250 };
251 i2c@1 { /* PMBUS1_INA226 */
252 #address-cells = <1>;
253 #size-cells = <0>;
254 reg = <1>;
255 /* FIXME check alerts coming to SC */
256 vccint: ina226@40 { /* u65 */
257 compatible = "ti,ina226";
258 #io-channel-cells = <1>;
259 label = "ina226-vccint";
260 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]261 shunt-resistor = <500>; /* R440 */
262 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]263 };
264 vcc_soc: ina226@41 { /* u161 */
265 compatible = "ti,ina226";
266 #io-channel-cells = <1>;
267 label = "ina226-vcc-soc";
268 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]269 shunt-resistor = <500>; /* R1702 */
270 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]271 };
272 vcc_pmc: ina226@42 { /* u163 */
273 compatible = "ti,ina226";
274 #io-channel-cells = <1>;
275 label = "ina226-vcc-pmc";
276 reg = <0x42>;
277 shunt-resistor = <5000>; /* R1214 */
278 /* 0.78V @ 500mA */
279 };
280 vcc_ram: ina226@43 { /* u162 */
281 compatible = "ti,ina226";
282 #io-channel-cells = <1>;
283 label = "ina226-vcc-ram";
284 reg = <0x43>;
285 shunt-resistor = <5000>; /* r1221 */
286 /* 0.78V @ 4A */
287 };
288 vcc_pslp: ina226@44 { /* u165 */
289 compatible = "ti,ina226";
290 #io-channel-cells = <1>;
291 label = "ina226-vcc-pslp";
292 reg = <0x44>;
293 shunt-resistor = <5000>; /* R1216 */
294 /* 0.78V @ 1A */
295 };
296 vcc_psfp: ina226@45 { /* u164 */
297 compatible = "ti,ina226";
298 #io-channel-cells = <1>;
299 label = "ina226-vcc-psfp";
300 reg = <0x45>;
301 shunt-resistor = <5000>; /* R1219 */
302 /* 0.78V @ 2A */
303 };
304 };
305 i2c@2 { /* PCIE_CLK */
306 #address-cells = <1>;
307 #size-cells = <0>;
308 reg = <2>;
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]309 clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]310 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
311 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]312 reg = <0x6c>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]313 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
314 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
315 };
316 };
317 i2c@3 { /* PMBUS2_INA226 */
318 #address-cells = <1>;
319 #size-cells = <0>;
320 reg = <3>;
321 /* FIXME check alerts coming to SC */
322 vccaux: ina226@40 { /* u166 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-vccaux";
326 reg = <0x40>;
327 shunt-resistor = <5000>; /* R382 */
328 /* 1.5V @ 3A */
329 };
330 vccaux_pmc: ina226@41 { /* u168 */
331 compatible = "ti,ina226";
332 #io-channel-cells = <1>;
333 label = "ina226-vccaux-pmc";
334 reg = <0x41>;
335 shunt-resistor = <5000>; /* R1246 */
336 /* 1.5V @ 500mA */
337 };
338 vcco_500: ina226@42 { /* u178 */
339 compatible = "ti,ina226";
340 #io-channel-cells = <1>;
341 label = "ina226-vcco-500";
342 reg = <0x42>;
343 shunt-resistor = <2000>; /* R1300 */
344 /* 3.3V @ 5A */
345 };
346 vcco_501: ina226@43 { /* u180 */
347 compatible = "ti,ina226";
348 #io-channel-cells = <1>;
349 label = "ina226-vcco-501";
350 reg = <0x43>;
351 shunt-resistor = <2000>; /* R1313 */
352 /* 3.3V @ 5A */
353 };
354 vcco_502: ina226@44 { /* u182 */
355 compatible = "ti,ina226";
356 #io-channel-cells = <1>;
357 label = "ina226-vcco-502";
358 reg = <0x44>;
359 shunt-resistor = <2000>; /* R1330 */
360 /* 3.3V @ 5A */
361 };
362 vcco_503: ina226@45 { /* u172 */
363 compatible = "ti,ina226";
364 #io-channel-cells = <1>;
365 label = "ina226-vcco-503";
366 reg = <0x45>;
367 shunt-resistor = <5000>; /* R1229 */
368 /* 1.8V @ 2A */
369 };
370 vcc_1v8: ina226@46 { /* u173 */
371 compatible = "ti,ina226";
372 #io-channel-cells = <1>;
373 label = "ina226-vcc-1v8";
374 reg = <0x46>;
375 shunt-resistor = <5000>; /* R400 */
376 /* 1.8V @ 6A */
377 };
378 vcc_3v3: ina226@47 { /* u174 */
379 compatible = "ti,ina226";
380 #io-channel-cells = <1>;
381 label = "ina226-vcc-3v3";
382 reg = <0x47>;
383 shunt-resistor = <5000>; /* R1232 */
384 /* 3.3V @ 500mA */
385 };
386 vcc_1v2_ddr4: ina226@48 { /* u176 */
387 compatible = "ti,ina226";
388 #io-channel-cells = <1>;
389 label = "ina226-vcc-1v2-ddr4";
390 reg = <0x48>;
391 shunt-resistor = <5000>; /* R1275 */
392 /* 1.2V @ 4A */
393 };
394 vcc1v1_lp4: ina226@49 { /* u177 */
395 compatible = "ti,ina226";
396 #io-channel-cells = <1>;
397 label = "ina226-vcc1v1-lp4";
398 reg = <0x49>;
399 shunt-resistor = <5000>; /* R1286 */
400 /* 1.1V @ 4A */
401 };
402 vadj_fmc: ina226@4a { /* u184 */
403 compatible = "ti,ina226";
404 #io-channel-cells = <1>;
405 label = "ina226-vadj-fmc";
406 reg = <0x4a>;
407 shunt-resistor = <2000>; /* R1350 */
408 /* 1.5V @ 10A */
409 };
410 mgtyavcc: ina226@4b { /* u186 */
411 compatible = "ti,ina226";
412 #io-channel-cells = <1>;
413 label = "ina226-mgtyavcc";
414 reg = <0x4b>;
415 shunt-resistor = <2000>; /* R1367 */
416 /* 0.88V @ 6A */
417 };
418 mgtyavtt: ina226@4c { /* u188 */
419 compatible = "ti,ina226";
420 #io-channel-cells = <1>;
421 label = "ina226-mgtyavtt";
422 reg = <0x4c>;
423 shunt-resistor = <2000>; /* R1384 */
424 /* 1.2V @ 10A */
425 };
426 mgtyvccaux: ina226@4d { /* u234 */
427 compatible = "ti,ina226";
428 #io-channel-cells = <1>;
429 label = "ina226-mgtyvccaux";
430 reg = <0x4d>;
431 shunt-resistor = <5000>; /* r1679 */
432 /* 1.5V @ 500mA */
433 };
434 };
435 i2c@4 { /* LP_I2C_SM */
436 #address-cells = <1>;
437 #size-cells = <0>;
438 reg = <4>;
439 /* FIXME wires ready but chip is missing */
440 };
441 i2c@5 { /* zSFP_SI570 */
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <5>;
445 si570_zsfp: clock-generator@5d { /* u192 */
446 #clock-cells = <0>;
447 compatible = "silabs,si570";
448 reg = <0x5d>;
449 temperature-stability = <50>;
450 factory-fout = <156250000>;
451 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]452 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]453 };
454 };
455 i2c@6 { /* USER_SI570_1 */
456 #address-cells = <1>;
457 #size-cells = <0>;
458 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]459 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]460 #clock-cells = <0>;
461 compatible = "silabs,si570";
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]462 reg = <0x5d>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]463 temperature-stability = <50>;
464 factory-fout = <100000000>;
465 clock-frequency = <100000000>;
466 clock-output-names = "si570_user1";
467 };
468
469 };
470 i2c@7 { /* USER_SI570_2 */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <7>;
474 /* FIXME wires ready but chip is missing */
475 };
476 };
477};
478
479&i2c1 { /* i2c1 MIO 36-37 */
480 status = "okay";
481 clock-frequency = <400000>;
482
483 i2c-mux@74 { /* u35 */
484 compatible = "nxp,pca9548";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]488 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]489 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
490 dc_i2c: i2c@0 { /* DC_I2C */
491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <0>;
494 /* Use for storing information about SC board */
495 eeprom: eeprom@54 { /* u34 - m24128 16kB */
496 compatible = "st,24c128", "atmel,24c128";
497 reg = <0x54>; /* 0x5c too */
498 };
499 si570_ref_clk: clock-generator@5d { /* u32 */
500 #clock-cells = <0>;
501 compatible = "silabs,si570";
502 reg = <0x5d>;
503 temperature-stability = <50>;
504 factory-fout = <33333333>;
505 clock-frequency = <33333333>;
506 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]507 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]508 };
509 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]510 eeprom_ebm: eeprom@52 { /* x-ebm module */
511 compatible = "st,24c128", "atmel,24c128";
512 reg = <0x52>;
513 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]514 };
515 fmc1: i2c@1 { /* FMCP1_IIC */
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <1>;
519 /* FIXME connection to Samtec J51C */
520 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]521 eeprom_fmc1: eeprom@50 {
522 compatible = "st,24c128", "atmel,24c128";
523 reg = <0x50>;
524 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]525 };
526 fmc2: i2c@2 { /* FMCP2_IIC */
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <2>;
530 /* FIXME connection to Samtec J53C */
531 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]532 eeprom_fmc2: eeprom@50 {
533 compatible = "st,24c128", "atmel,24c128";
534 reg = <0x50>;
535 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]536 };
537 i2c@3 { /* DDR4_DIMM1 */
538 #address-cells = <1>;
539 #size-cells = <0>;
540 reg = <3>;
541 si570_ddr_dimm1: clock-generator@60 { /* u2 */
542 #clock-cells = <0>;
543 compatible = "silabs,si570";
544 reg = <0x60>;
545 temperature-stability = <50>;
546 factory-fout = <200000000>;
547 clock-frequency = <200000000>;
548 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]549 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]550 };
551 };
552 i2c@4 { /* LPDDR4_SI570_CLK2 */
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]556 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]557 #clock-cells = <0>;
558 compatible = "silabs,si570";
559 reg = <0x60>;
560 temperature-stability = <50>;
561 factory-fout = <200000000>;
562 clock-frequency = <200000000>;
563 clock-output-names = "si570_lpddr4_clk2";
564 };
565 };
566 i2c@5 { /* LPDDR4_SI570_CLK1 */
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]570 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]571 #clock-cells = <0>;
572 compatible = "silabs,si570";
573 reg = <0x60>;
574 temperature-stability = <50>;
575 factory-fout = <200000000>;
576 clock-frequency = <200000000>;
577 clock-output-names = "si570_lpddr4_clk1";
578 };
579 };
580 i2c@6 { /* HSDP_SI570 */
581 #address-cells = <1>;
582 #size-cells = <0>;
583 reg = <6>;
584 si570_hsdp: clock-generator@5d { /* u5 */
585 #clock-cells = <0>;
586 compatible = "silabs,si570";
587 reg = <0x5d>;
588 temperature-stability = <50>;
589 factory-fout = <156250000>;
590 clock-frequency = <156250000>;
591 clock-output-names = "si570_hsdp_clk";
592 };
593 };
594 i2c@7 { /* 8A34001 - U219B and J310 connector */
595 #address-cells = <1>;
596 #size-cells = <0>;
597 reg = <7>;
598 };
599 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]600 i2c-mux@75 { /* u214 */
601 compatible = "nxp,pca9548";
602 #address-cells = <1>;
603 #size-cells = <0>;
604 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]605 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]606 i2c@0 { /* SFP0_IIC */
607 #address-cells = <1>;
608 #size-cells = <0>;
609 reg = <0>;
610 /* SFP0 */
611 };
612 i2c@1 { /* SFP1_IIC */
613 #address-cells = <1>;
614 #size-cells = <0>;
615 reg = <1>;
616 /* SFP1 */
617 };
618 i2c@2 { /* QSFP1_I2C */
619 #address-cells = <1>;
620 #size-cells = <0>;
621 reg = <2>;
622 /* QSFP1 */
623 };
624 /* 3 - 7 unused */
625 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]626};
627
628&xilinx_ams {
629 status = "okay";
630};
631
632&ams_ps {
633 status = "okay";
634};
635
636&ams_pl {
637 status = "okay";
638};