| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * NXP LS1028A-QDS device tree fragment for RCW 1xxx |
| 4 | * |
| Vladimir Oltean | 5041e42 | 2021-09-17 14:27:13 +0300 | [diff] [blame] | 5 | * Copyright 2019-2021 NXP |
| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC |
| 10 | * port 0 USXGMII. |
| 11 | */ |
| 12 | &slot1 { |
| 13 | #include "fsl-sch-30842.dtsi" |
| 14 | }; |
| 15 | |
| Michael Walle | 2a20ed1 | 2021-10-13 18:14:15 +0200 | [diff] [blame] | 16 | &enetc_port0 { |
| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 17 | status = "okay"; |
| Vladimir Oltean | 1526ba5 | 2022-01-03 14:47:37 +0200 | [diff] [blame] | 18 | managed = "in-band-status"; |
| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 19 | phy-mode = "usxgmii"; |
| Michael Walle | 2da16cd | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 20 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; |
| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 21 | }; |