| Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Marvell International Ltd. and its affiliates |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DDR_TOPOLOGY_DEF_H |
| 8 | #define _DDR_TOPOLOGY_DEF_H |
| 9 | |
| 10 | #include "ddr3_training_ip_def.h" |
| 11 | #include "ddr3_topology_def.h" |
| 12 | |
| 13 | #if defined(CONFIG_ARMADA_38X) |
| 14 | #include "ddr3_a38x.h" |
| 15 | #endif |
| 16 | |
| 17 | /* bus width in bits */ |
| 18 | enum hws_bus_width { |
| 19 | BUS_WIDTH_4, |
| 20 | BUS_WIDTH_8, |
| 21 | BUS_WIDTH_16, |
| 22 | BUS_WIDTH_32 |
| 23 | }; |
| 24 | |
| 25 | enum hws_temperature { |
| 26 | HWS_TEMP_LOW, |
| 27 | HWS_TEMP_NORMAL, |
| 28 | HWS_TEMP_HIGH |
| 29 | }; |
| 30 | |
| 31 | enum hws_mem_size { |
| 32 | MEM_512M, |
| 33 | MEM_1G, |
| 34 | MEM_2G, |
| 35 | MEM_4G, |
| 36 | MEM_8G, |
| 37 | MEM_SIZE_LAST |
| 38 | }; |
| 39 | |
| 40 | struct bus_params { |
| 41 | /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ |
| 42 | u8 cs_bitmask; |
| 43 | |
| 44 | /* |
| 45 | * mirror enable/disable |
| 46 | * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...) |
| 47 | */ |
| 48 | int mirror_enable_bitmask; |
| 49 | |
| 50 | /* DQS Swap (polarity) - true if enable */ |
| 51 | int is_dqs_swap; |
| 52 | |
| 53 | /* CK swap (polarity) - true if enable */ |
| 54 | int is_ck_swap; |
| 55 | }; |
| 56 | |
| 57 | struct if_params { |
| 58 | /* bus configuration */ |
| 59 | struct bus_params as_bus_params[MAX_BUS_NUM]; |
| 60 | |
| 61 | /* Speed Bin Table */ |
| 62 | enum hws_speed_bin speed_bin_index; |
| 63 | |
| 64 | /* bus width of memory */ |
| 65 | enum hws_bus_width bus_width; |
| 66 | |
| 67 | /* Bus memory size (MBit) */ |
| 68 | enum hws_mem_size memory_size; |
| 69 | |
| 70 | /* The DDR frequency for each interfaces */ |
| 71 | enum hws_ddr_freq memory_freq; |
| 72 | |
| 73 | /* |
| 74 | * delay CAS Write Latency |
| 75 | * - 0 for using default value (jedec suggested) |
| 76 | */ |
| 77 | u8 cas_wl; |
| 78 | |
| 79 | /* |
| 80 | * delay CAS Latency |
| 81 | * - 0 for using default value (jedec suggested) |
| 82 | */ |
| 83 | u8 cas_l; |
| 84 | |
| 85 | /* operation temperature */ |
| 86 | enum hws_temperature interface_temp; |
| 87 | }; |
| 88 | |
| 89 | struct hws_topology_map { |
| 90 | /* Number of interfaces (default is 12) */ |
| 91 | u8 if_act_mask; |
| 92 | |
| 93 | /* Controller configuration per interface */ |
| 94 | struct if_params interface_params[MAX_INTERFACE_NUM]; |
| 95 | |
| 96 | /* BUS per interface (default is 4) */ |
| 97 | u8 num_of_bus_per_interface; |
| 98 | |
| 99 | /* Bit mask for active buses */ |
| 100 | u8 bus_act_mask; |
| 101 | }; |
| 102 | |
| 103 | /* DDR3 training global configuration parameters */ |
| 104 | struct tune_train_params { |
| 105 | u32 ck_delay; |
| 106 | u32 ck_delay_16; |
| 107 | u32 p_finger; |
| 108 | u32 n_finger; |
| 109 | u32 phy_reg3_val; |
| 110 | }; |
| 111 | |
| 112 | #endif /* _DDR_TOPOLOGY_DEF_H */ |