blob: a340e97f008c61cc739a544daa1e72d22d7fff35 [file] [log] [blame]
Sascha Hauerce6fc522008-03-26 20:41:09 +01001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
Magnus Lilja69e84582008-04-15 19:09:10 +02007 * Configuration settings for the LogicPD i.MX31 Litekit board.
Sascha Hauerce6fc522008-03-26 20:41:09 +01008 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Stefano Babic78129d92011-03-14 15:43:56 +010031#include <asm/arch/imx-regs.h>
Magnus Liljad1948c62008-04-20 10:36:36 +020032
Sascha Hauerce6fc522008-03-26 20:41:09 +010033 /* High Level Configuration Options */
34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35#define CONFIG_MX31 1 /* in a mx31 */
36#define CONFIG_MX31_HCLK_FREQ 26000000
37#define CONFIG_MX31_CLK32 32000
38
39#define CONFIG_DISPLAY_CPUINFO
40#define CONFIG_DISPLAY_BOARDINFO
41
Fabio Estevamddc647f2011-06-06 03:13:36 +000042#define CONFIG_SYS_TEXT_BASE 0xa0000000
43
Fabio Estevama0f47112011-09-22 08:07:17 +000044#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
45
Sascha Hauerce6fc522008-03-26 20:41:09 +010046/* Temporarily disabled */
47#if 0
48#define CONFIG_OF_LIBFDT 1
49#define CONFIG_FIT 1
50#define CONFIG_FIT_VERBOSE 1
51#endif
52
53#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
54#define CONFIG_SETUP_MEMORY_TAGS 1
55#define CONFIG_INITRD_TAG 1
56
57/*
58 * Size of malloc() pool
59 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Sascha Hauerce6fc522008-03-26 20:41:09 +010061
62/*
63 * Hardware drivers
64 */
65
Stefano Babic1ca47d92011-11-22 15:22:39 +010066#define CONFIG_MXC_UART
67#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic39069902011-08-26 11:54:05 +020068#define CONFIG_MXC_GPIO
Sascha Hauerce6fc522008-03-26 20:41:09 +010069
Magnus Lilja180381d2008-04-20 10:38:12 +020070#define CONFIG_HARD_SPI 1
71#define CONFIG_MXC_SPI 1
Haavard Skinnemoend74084a2008-05-16 11:10:31 +020072#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic4c596992010-08-23 20:41:19 +020073#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Lilja180381d2008-04-20 10:38:12 +020074
Stefano Babic0e9aa0e2011-10-08 11:01:52 +020075/* PMIC Controller */
76#define CONFIG_PMIC
77#define CONFIG_PMIC_SPI
78#define CONFIG_PMIC_FSL
Stefano Babice0432032010-04-16 17:11:19 +020079#define CONFIG_FSL_PMIC_BUS 1
80#define CONFIG_FSL_PMIC_CS 0
81#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic4c596992010-08-23 20:41:19 +020082#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic0e9aa0e2011-10-08 11:01:52 +020083#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam3f8d1782011-10-24 06:44:15 +000084#define CONFIG_RTC_MC13XXX
Magnus Lilja180381d2008-04-20 10:38:12 +020085
Sascha Hauerce6fc522008-03-26 20:41:09 +010086/* allow to overwrite serial and ethaddr */
87#define CONFIG_ENV_OVERWRITE
88#define CONFIG_CONS_INDEX 1
89#define CONFIG_BAUDRATE 115200
Sascha Hauerce6fc522008-03-26 20:41:09 +010090
91/***********************************************************
92 * Command definition
93 ***********************************************************/
94
95#include <config_cmd_default.h>
96
97#define CONFIG_CMD_MII
98#define CONFIG_CMD_PING
Magnus Lilja180381d2008-04-20 10:38:12 +020099#define CONFIG_CMD_SPI
100#define CONFIG_CMD_DATE
Magnus Lilja065d5592010-04-23 20:30:49 +0200101#define CONFIG_CMD_NAND
Sascha Hauerce6fc522008-03-26 20:41:09 +0100102
103#define CONFIG_BOOTDELAY 3
104
105#define CONFIG_NETMASK 255.255.255.0
106#define CONFIG_IPADDR 192.168.23.168
107#define CONFIG_SERVERIP 192.168.23.2
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
111 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
112 "bootcmd=run bootcmd_net\0" \
113 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
114 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
115
116
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700117#define CONFIG_SMC911X 1
118#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
119#define CONFIG_SMC911X_32_BIT 1
Sascha Hauerce6fc522008-03-26 20:41:09 +0100120
121/*
122 * Miscellaneous configurable options
123 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_LONGHELP /* undef to save memory */
125#define CONFIG_SYS_PROMPT "uboot> "
126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100127/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
129#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x10000
Sascha Hauerce6fc522008-03-26 20:41:09 +0100134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_HZ 1000
Sascha Hauerce6fc522008-03-26 20:41:09 +0100138
139#define CONFIG_CMDLINE_EDITING 1
140
141/*-----------------------------------------------------------------------
142 * Stack sizes
143 *
144 * The stack sizes are set up in start.S using the settings below
145 */
146#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
147
148/*-----------------------------------------------------------------------
149 * Physical Memory Map
150 */
151#define CONFIG_NR_DRAM_BANKS 1
Magnus Liljad1948c62008-04-20 10:36:36 +0200152#define PHYS_SDRAM_1 CSD0_BASE
Sascha Hauerce6fc522008-03-26 20:41:09 +0100153#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevam6ddd7232011-06-05 14:56:02 +0000154#define CONFIG_BOARD_EARLY_INIT_F
Sascha Hauerce6fc522008-03-26 20:41:09 +0100155
Fabio Estevamd23e65f2011-09-22 08:07:13 +0000156#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Magnus Liljada87d1e2010-10-16 19:47:06 +0200157#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200158#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Wolfgang Denk0191e472010-10-26 14:34:52 +0200159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Magnus Liljada87d1e2010-10-16 19:47:06 +0200160#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
161
Sascha Hauerce6fc522008-03-26 20:41:09 +0100162/*-----------------------------------------------------------------------
163 * FLASH and environment organization
164 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_BASE CS0_BASE
166#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
167#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200171#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200172#define CONFIG_ENV_SECT_SIZE (64 * 1024)
173#define CONFIG_ENV_SIZE (64 * 1024)
Sascha Hauerce6fc522008-03-26 20:41:09 +0100174
175/*-----------------------------------------------------------------------
176 * CFI FLASH driver setup
177 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200179#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
181#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100182
183/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
185#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Sascha Hauerce6fc522008-03-26 20:41:09 +0100186
187/*
188 * JFFS2 partitions
189 */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100190#undef CONFIG_CMD_MTDPARTS
Sascha Hauerce6fc522008-03-26 20:41:09 +0100191#define CONFIG_JFFS2_DEV "nor0"
192
Magnus Lilja065d5592010-04-23 20:30:49 +0200193/*
194 * NAND flash
195 */
196#define CONFIG_NAND_MXC
197#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
198#define CONFIG_SYS_MAX_NAND_DEVICE 1
199#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
200#define CONFIG_MXC_NAND_HWECC
201
Sascha Hauerce6fc522008-03-26 20:41:09 +0100202#endif /* __CONFIG_H */