Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | * Written by Simon Glass <sjg@chromium.org> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 10 | #include <asm/arch/iomap.h> |
Bernhard Messerklinger | d9461aa | 2020-05-18 12:33:34 +0200 | [diff] [blame] | 11 | #include <asm/arch/fsp_bindings.h> |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 12 | #include <asm/fsp2/fsp_internal.h> |
| 13 | #include <dm/uclass-internal.h> |
| 14 | |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 15 | int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) |
| 16 | { |
| 17 | struct fsp_m_config *cfg = &upd->config; |
| 18 | struct fspm_arch_upd *arch = &upd->arch; |
Simon Glass | 1d2a334 | 2020-07-09 18:43:17 -0600 | [diff] [blame] | 19 | int cache_ret = 0; |
Bernhard Messerklinger | d9461aa | 2020-05-18 12:33:34 +0200 | [diff] [blame] | 20 | ofnode node; |
Simon Glass | 1d2a334 | 2020-07-09 18:43:17 -0600 | [diff] [blame] | 21 | int ret; |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 22 | |
| 23 | arch->nvs_buffer_ptr = NULL; |
Simon Glass | 1d2a334 | 2020-07-09 18:43:17 -0600 | [diff] [blame] | 24 | cache_ret = prepare_mrc_cache(upd); |
| 25 | if (cache_ret && cache_ret != -ENOENT) |
| 26 | return log_msg_ret("mrc", cache_ret); |
Simon Glass | c28a1e0 | 2020-07-16 21:22:33 -0600 | [diff] [blame^] | 27 | arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - |
| 28 | arch->stack_size); |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 29 | arch->boot_loader_tolum_size = 0; |
Simon Glass | a929b93 | 2020-07-16 21:22:32 -0600 | [diff] [blame] | 30 | arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION : |
| 31 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 32 | |
Bernhard Messerklinger | d9461aa | 2020-05-18 12:33:34 +0200 | [diff] [blame] | 33 | node = dev_ofnode(dev); |
| 34 | if (!ofnode_valid(node)) |
| 35 | return log_msg_ret("fsp-m settings", -ENOENT); |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 36 | |
Simon Glass | 1d2a334 | 2020-07-09 18:43:17 -0600 | [diff] [blame] | 37 | ret = fsp_m_update_config_from_dtb(node, cfg); |
| 38 | if (ret) |
| 39 | return log_msg_ret("dtb", cache_ret); |
| 40 | |
| 41 | return cache_ret; |
Simon Glass | 42bf7db | 2019-12-08 17:40:19 -0700 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | /* |
| 45 | * The FSP-M binary appears to break the SPI controller. It can be fixed by |
| 46 | * writing the BAR again, so do that here |
| 47 | */ |
| 48 | int fspm_done(struct udevice *dev) |
| 49 | { |
| 50 | struct udevice *spi; |
| 51 | int ret; |
| 52 | |
| 53 | /* Don't probe the device, since that reads the BAR */ |
| 54 | ret = uclass_find_first_device(UCLASS_SPI, &spi); |
| 55 | if (ret) |
| 56 | return log_msg_ret("SPI", ret); |
| 57 | if (!spi) |
| 58 | return log_msg_ret("no SPI", -ENODEV); |
| 59 | |
| 60 | dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0, |
| 61 | IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 62 | |
| 63 | return 0; |
| 64 | } |